Engineer Design

Title:Edward Taub

abps75@r.postjobfree.com

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Name: Edward Taub

Address:

City: Mountain View

State: CA

Zip/Postal Code: 94041

Country:

E-mail: abps75@r.postjobfree.com

Primary Phone:

Background

Most Recent Job Title: Hardware Design Engineer

Most Recent Employer: Cisco

Career Level: Associate/Experienced (Non-Manager)

Availability or Timeframe: Immediately

Authorized to work in the US: Yes

Security Clearance:

Do you have transportation: Yes

Over 18: Yes

Education: Masters

Languages Spoken: English

Job Preferences

Desired Salary: Open

Willing to Relocate:

Desired Job Titles:

Desired Job Types: Employee

Work Status: Full Time

Desired Shifts: 1st Shift

Desired Travel:

Category: Engineering and Research

Company Size:

Company Type:

Industry: Computers Software and Hardware, Electronics, Energy / Utilities / Oil & Gas,

Engineering, Telecommunications

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Copyright c 1997- Lee Hecht Harrison, Inc.

EDWARD S. TAUB

822 Devoto Street 650-***-****

Mountain View CA 94041 abps75@r.postjobfree.com

Linkedin profile: http://www.linkedin.com/in/edtaub

SUMMARY

Hardware design engineer with a strong background in embedded communication system design

and

development. Successful developer of data communication and networking products at the

system, board,

and FPGA levels. Recent system engineering experience at Cisco Systems involved

application of the

latest technologies (high speed memories, standard digital interfaces and advanced

ASIC/FPGA devices)

to create solutions for difficult technical challenges.

SKILLS

HW Design:

Languages: Verilog HDL

Logic Synthesis: Synplify; Synopsys (Design Compiler, FPGA Compiler)

Design Verification:

Languages: systemVerilog; Vera

Tools: VCS simulator; Verilog-XL simulator; Verdi waveform viewer/checker; Xilinx,

Synopsys Static

Timing Analyzer; Oscilloscope; Logic Analyzer

HW Emulation: Xilinx XC4013-based emulator

SW Design:

Languages: C++, C, 8051 Assembler

PROFESSIONAL EXPERIENCE

CISCO SYSTEMS, San Jose CA 1996 - 2009Hardware Engineer

GSBU:

2003

- Oct. 2009

Verified Wireless Protocol Converter FPGA subsystem used to convert between existing

Ethernet 802.3 packet

formats and WiFi/802.11/CAPWAP protocols. Developed systemVerilog OOP constrained random

testbench to

generate/check complex LAN protocol conversions. Exhaustively verified all valid packet

types/functional modes using advanced systemVerilog constraints to

maximize protocol coverage.

Innovated use of behavior model as RTL stimulus source to replace defective verilog HW

modules. This

allowed us to work around obstacles and meet tight deadlines.

Innovated use of gcov tool to provide functional coverage estimates to assess test

completeness.

Verified two generations of Cisco Cat4500 Switch Supervisor Board via simulation of board

schematic

netlist/embedded ASIC verilog models.

Project detected and corrected numerous board defects thereby accelerating Product

Release.

Generated functional specification of advanced 144 bit wide Cisco DDR SRAM with highest

bandwidth available

(1.3Gbps per pin) Developed executable verilog model used by CSRAM vendors to confirm

that their devices met Cisco spec

requirements

CSRAM is currently shipping in every Catalyst 4500 switch

Integrated verilog CSRAM model into next generation Catalyst 4500 system verification

environment.

Model detected problems in ASIC controller avoiding costly silicon re-spins.

Optical BU/DWDM

(Dense Wavelength Division Multiplexing): 2000 - 2003

Successfully completed and shipped a number of FPGA based switch products.

Edward Taub Page 1

Developed Protection Switching Module (PSM) FPGA used to detect low light levels and

provide automatic

protection switching capabilities for redundant optical trunk selection. FCS occurred in

minimal time with no

known defects.

Developed RPG/RPM FPGA which was used as part of redundancy control logic for XGMII

data path used in

10G Ethernet DWDM trunk card.

Metropolitan Networking BU

: 1998 - 2000:

Leader of a 3 person HW/SW team which developed a Traffic Shaping Carrier Module (TSCAM-

8510).

Module added a 32k vc Traffic shaping capability to the Catalyst 8510 ATM switch

platform. I designed a

490k gate Xilinx XCV600E FPGA which performed interface conversion between the switch

backplane and a

commercial traffic shaping ASIC from PMC-Sierra. The product was delivered defect free

and is currently

shipping as a Cisco product.

Small Internetworking BU (SIBU): 1996 -1998:

Verified high-performance version of C2900-XL Switch fabric chip.

. Verified VLAN-capable version of C2900-XL eight port Ethernet controller chip.

Performed verilog system simulation of a Fast Ethernet Switch chipset used in Catalyst

2900XL Ethernet switch.

Responsible for early HW integration of chipset in the Lab.

Developed menu-driven HW functional test suite in C for use in Lab bringup and

manufacturing test.

Wide Area Networking BU (WANBU/StrataCom): 1996

Responsible for design/development of a Utopia Data Processing ASIC needed to support

multi-port ATM

operation at DS3 rate (44.7 Mbps). Synthesizable model generated in Verilog HDL. Chip

was fully functional on first pass of Silicon.

Shipped on BPX switch as part of multi-port T3 concentrator.

Previous Positions Include:

Hardware Engineer, CIRRUS LOGIC, Fremont CA

Chief Engineer

for parallel port projects including CL-CD1284 product (20k gate IEEE-1284

compliant parallel

port printer controller). Accomplished chip subsystem integration using innovative

Xilinx HW emulation of complex verilog protocol

state machine. My method led to a fully compliant chip on the first pass of Silicon.

Member of the Technical Staff, ROLM SYSTEMS,

Santa Clara CA

Core Engineering Development: Phonemail Diagnostics: CBX HW Systems Engineering.

Technical Staff Member, IBM Federal Systems Div., Gaithersburg MD

- Gaithersburg Lab: Developed Test Equipment for Space Telescope (NASA); Hardware Systems

Engineer:

AAS Air Traffic Control system upgrade (FAA)

- Manassas Lab: HW Designer (Intelligent (microprocesssor based) Serial I/O subsystem for

AN/UYK-44 Navy

Computer)

EDUCATION

M.S

. (Comp. Sci), George Washington University, Washington, D.C.

BSEE,

Columbia University School of Engineering, NYC

Selected Publications

ASIC Verification across Multiple Development Environments Proceedings, Design

SuperCon'95 On-Chip System

Design Conference

Design of Complex State Machines PLDCon 1995

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