Design Project

Arvind Sudarsanam

*** *. *** *, *****, UT ***** 435-***-**** **************@*****.***

JOB OBJECTIVE

Full-time or Intern position in the field of digital design with an opportunity to be

involved with emerging and disruptive technologies

RESEARCH INTERESTS

FPGAs, Reconfigurable computing, Compiler construction, Memory design, Computer

architectures.

EDUCATION

Ph.D. Electrical Engineering, Utah State University, Sep 2004 - Present

Dissertation KF-ESL: An FPGA-based ESL tool flow to automatically design SoC

circuits for Kalman Filters

M.S. Electrical Engineering, Arizona State University, Sep 2001 - Aug. 2004

GPA 3.6 / 4.0

Masters Thesis Dynamic Memory Management and Scheduling for Reconfigurable

Media Processing

Course work in VLSI system-level design and hardware design, VHDL, digital

design and algorithms.

Research Assistant under Dr. S. Panchanathan and worked in projects involving

Intel s SSE2 technology and network processors.

B.E. Electronics and Instrumentation, BITS, Pilani, India, Sep 1997 - Jun. 2001

GPA 3.53 / 4.0

Senior Project Speech recognition and lip reading algorithms

Course work in DSP and Image Processing, microcontroller, analog and digital

design.

WORK EXPERIENCE

Intel Corporation (June 2008 August 2008)

Graduate Intern in the Visual Computing Group, Hillsboro, OR

Summer project towards developing a reconfigurable motion estimation accelerator

towards Intel s Larrabee

Utah State University (Aug 2006 Present)

Research Assistant under Dr. Aravind Dasu

Three-year project on developing an automated ESL tool flow for Kalman Filters

(Sponsored by NASA)

Utah State University (Aug 2005 Aug 2006)

Research Assistant under Dr. Aravind Dasu

One-year project on implementing LU Decomposition for large matrices using Viva

(Sponsored by Lockheed Martin)

Utah State University (Aug 2004 Aug 2005)

Research Assistant under Dr. Aravind Dasu

One-year project on implementing matrix and signal processing algorithms for

Starbridge Hypercomputer using Viva

(Sponsored by Starbridge Systems)

Arizona State University (Aug 2001 Aug 2004)

Research Assistant under Dr. Sethuraman Panchanathan

One-year project (2001-02) on implementing video transcoding algorithms for Intel

IXP1200 Network Processors (Sponsored by Center for Embedded and

InterNetworking Technologies, a collaborative research by Intel and Motorola)

One-year project (2002-03) on implementing signal and image processing and

communications algorithms optimized for Intel SSE2 technology. (Sponsored by

Center for Embedded and InterNetworking Technologies, a collaborative research by

Intel and Motorola)

Texas Instruments (Jan 2001 Jun 2001)

Intern with the OMAP (Open Multimedia Application Platform) team.

6 month project for optimizing algorithms for video preprocessing on TI C5510 DSP.

JOURNALS (In chronological order)

1. A. Dasu, A. Sudarsanam, S. Panchanathan, Design of Embedded Compute Intensive

Processing Elements and their Scheduling in a Reconfigurable Environment, in the

Canadian Journal of Electrical and Computer Engineering (CJECE), 2005.

2. T. Hauser, A. Dasu, A. Sudarsanam, and S. Young, Performance of LU decomposition

on a Multi-FPGA System Compared to a Low Power Commodity Microprocessor

System, in the journal for Scalable computing: Practice and Experience, 2007, Vol 8, No

4.

3. J. Phillips, A. Sudarsanam, R. Kallam, J. Carver, and A. Dasu, Methodology to Derive

Polymorphic Soft-IP Cores for FPGAs, in the journal of IET Computers & Digital

Techniques, 2008.

4. A. Sudarsanam, T. Hauser, A. Dasu, and S. Young, A Power Efficient Linear

Equation Solver on a Multi-FPGA Accelerator, accepted for publication in the

International Journal of Computers and Applications, 2009.

5. A. Sudarsanam, R. Barnes, R. Kallam, J. Carver, and A. Dasu, Dynamically

Reconfigurable Systolic Array Accelerators: A Case Study with EKF and DWT

Algorithms, accepted for publication in the journal of IET Computers & Digital

Techniques, 2009.

6. A. Sudarsanam, A. Dasu, and K. Vaithianathan, Analysis and Design of a Context

Adaptable SAD/MSE Accelerator, submitted to the International Journal of

Reconfigurable Computing, 2009.

CONFERENCES (In chronological order)

1. A. Akoglu, A. Dasu, A. Sudarsanam, M. Srinivasan, S. Panchanathan, Pattern

recognition tool to detect reconfigurable patterns in MPEG4 video processing, in the

IEEE Proceedings of Parallel and Distributed Processing Symposium, 2002.

2. A. Sudarsanam, S. Panchanathan, Current Trends for Silicon and Embedded

Computing Solutions for Automotive Applications, in the Proceedings of the

convergence conference of SAE, Detroit, October, 2002.

3. A. Sudarsanam, A. Dasu, S. Panchanathan, Task Scheduling of Control Data Flow

Graphs for Reconfigurable Architectures, in the Proceedings of the International

Conference on Engineering of Reconfigurable Systems and Algorithms, 2004.

4. A. Sudarsanam, M.Srinivasan, S. Panchanathan, Resource Estimation and Task

Scheduling for Multithreaded Reconfigurable Architectures, in the Proceedings of the

International Conference on Parallel and Distributed Systems (ICPADS 2004).

5. A. Sudarsanam. S, Panchanathan, Novel predicated data flow analysis based memory

design for data and control intensive multimedia applications, in the Proceedings of the

SPIE conference on Electronic Imaging, 2005.

6. A. Sudarsanam, A. Dasu, High Level - Application Analysis Techniques &

Architectures - to Explore Design possibilities for Reduced Reconfiguration Area

Overheads in FPGAs executing Compute Intensive Applications, in the Proceedings of

the Reconfigurable Architectures Workshop (RAW), 2005.

7. A. Sudarsanam, A. Dasu, Implementation of Polymorphic Matrix Inversion using

Viva, presented at the MAPLD conference, 2005.

8. A. Sudarsanam, A. Dasu, A Fast and Efficient FPGA-Based Implementation for

Solving a System of Linear Interval Equations, in the IEEE Proceedings of the

conference on Field Programmable Technology (FPT), 2005.

9. A. Sudarsanam, S. Young, T. Hauser, and A. Dasu, Multi FPGA based High

Performance LU Decomposition, in the Proceedings of the High Performance

Embedded Computing workshop (HPEC), 2006.

10. S. Young, A. Sudarsanam, T. Hauser, and A. Dasu, Memory Support Design for LU

Decomposition on Starbridge Hypercomputer, in the IEEE Proceedings of the

conference on Field Programmable Technology (FPT), 2006.

PATENTS

Patent pending on Methodology to Design a Reconfigurable Processor

COURSE PROJECTS

VLSI design of a VLIW processor

FPGA-based hardware design for solving a system of linear interval equations

Layout design of Pseudo Random Number Generator using Tanner tools

VLSI architecture for MPEG-4 Sprite decoder

VHDL design of JPEG encoder

Matlab design of Multi-Resolution Motion Estimation

Analysis of MPEG-4 Motion Estimation Algorithm with the Two Level Top-Down

Partitioning Approach.

Speech recognition and Lip reading using Hidden Markov Models.

COMPUTER SKILLS

Operating Systems: Windows, Unix, DOS

Programming Languages: VHDL, C/C++, Assembly (IXP1200, SSE2, AltiVec,

TMS320C55x, ARM), Matlab, Viva.

Tools: Xilinx tools, Cadence HDL synthesis, Intel s IPP, TI code composer studio,

Tanner tools

Compilers: GNU C compiler, Lance compiler and Intel C++ compiler.

REFERENCES

Dr. Sethuraman Panchanathan; Dr. Aravind Dasu

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