Lai, Liangzhen

***** ******* *** *** ***, Torrance, CA 90504

abpn3c@r.postjobfree.com

www.ee.ucla.edu/~liangzhe

Research Design for Manufacturability Electronic Design Automation Resilient Architecture

Thermal-Aware Design Variability Monitors

Interests

Education

2006-2010 HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY (HKUST)

Admitted with full Scholarship

Bachelor of Engineering in Electronic Engineering (Honors Research Option)

First Class Honors

Minor Degree in Mathematics

2010-present UNIVERSITY OF CALIFORNIA, LOS ANGELES (UCLA)

Admitted to MS/PHD program in Electrical Engineering Department

Research Experience and Projects

Oct 2010

DESIGN-DEPENDENT RING OSCILLATORS

Oct 2011

Project Objective: Implement a performance monitoring methodology that systematically designs and

exploits multiple design-dependent ring-oscillators Supervisors: Puneet Gupta and Andrew Kahng

Ongoing and Future Work: We had a testchip tape-out with ARM Cortex-M3 using 45nm SOI in Feb.

2011. We are going to integrate the monitoring methodology with software and operating system

controls.

Publication: Tuck Boon Chan, Puneet Gupta, Andrew Kahng and Liangzhen Lai, DDRO: A Novel Performance

Monitoring Methodology Based on Design-Dependent Ring Oscillators, in Proc. IEEE International

Symposium on Quality Electronic Design (ISQED) 2012

Feb 2011 EVALUATE DEVICE VARIATIONS ON CIRCUIT BENCHMARKS

May 2012

Project Objective: Implement an automatic flow to evaluate the impact of device-level variations on

circuit-level performance Supervisors: Chi On Chui and Puneet Gupta

Project Overview: We implement an evaluation flow which takes device-level performance figure

variations as input, generates compact device model samples and corresponding standard cell libraries.

The libraries can be used for circuit-level performance analysis by conventional timing and power

analysis tools.

Publication: Gregory Leung, Liangzhen Lai, Chi On Chui and Puneet Gupta, Device and Circuit Level Variability

Caused by Line Edge Roughness for Sub-32nm Finfet Technologies, IEEE Transactions on Electronic

Devices, vol. 59, pp. 2057 -2063, aug. 2012

June 2009

FINAL YEAR THESIS (FYT)

Aug 2010

Thesis Topic: Interconnect Layer Thermal Modeling for 3D ICs Supervisor: Chi-Ying TSUI

Abstract: Interconnect Layer is essential for on-chip heat removal of 3D ICs. This project aims at

modeling the interconnect layer and abstracting the equivalent thermal resistance to facilitate thermal

simulation from the architecture level.

Publication: Liangzhen Lai, Hua Ding, Chi-Ying Tsui, Analysis of the Heat Removal Capability of the Power

Distribution Network in 3-D ICs, International Microsysstems, Packaging, Assembly and Circuits

Technology, pp. 1-4, Oct. 2010

Hua Ding, Wei Wang, Zhiliang Qian, Chi-Ying Tsui, and Liangzhen Lai, Thermal Modeling

of Three-Dimensional Integrated Circuits Considering the Thermal Removal Capability of

Different TSVs, in the proceedings of 3rd Asia Symposium on Quality Electronic Design (ASQED2011)

July 2011

Work Experience

June 2012 Summer Intern at ARM Inc. San Jose

Sept 2012

Project Title: Low Overhead In Situ Monitoring Methodology Mentor : Vikas Chandra

Abstract: In situ monitoring is an accurate way to monitor circuit delay, but usually incur significant

overhead. We propose and develop a novel methodology of monitoring circuit internal nodes.

Experiments on commercial processors show that our method can reduce the number of monitors by an

order of magnitude

Publication: Liangzhen Lai, Vikas Chandra, Robert Aitken and Puneet Gupta, SlackProbe: A Low Overhead In

Situ On-line Timing Slack Monitoring Methodology, accepted by Design, Automation, and Test in

Europe (DATE) 2013

Scholarship and Awards

2005 NATIONAL PHYSICS COMPETITION

First Prize in Fujian Province

2006-2010 UNIVERSITY SCHOLARSHIP

Awarded by Hong Kong University of Science & Technology

2006-2010 SCHOOL OF ENGINEERING SCHOLARSHIP

Awarded by School of Engineering, HKUST

2006-2010 ECE OUTSTANDING FRESHMEN SCHOLARSHIP

Awarded by Electronic and Engineering Department, HKUST

2006-2010 DEAN S LIST

Awarded by Engineering Dean s Office for excellent academic performance

Skills

Programming C/C++, MATLAB, PERL

EDA Tools CALIBRE, VIRTUOSO, ENCOUNTER, DESIGN COMPILER, HSPICE

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