Test Design

Dr. Sandeep Kumar Goel

**** ******** *****, **** ****,

San Jose, CA 95134, USA

Email:abpkr4@r.postjobfree.com

Personal

DOB: 31 August 1976, Nationality: Indian

Languages: English (G), Dutch (B)

Value 11 years of research and engineering program management experience for big corporations across

Europe, USA, and Asia. Proven success in innovation and management for research, semiconductor, EDA

Proposition

and foundry companies. Strong interpersonal, communication and problem solving skills.

Work Experience

2010-present Taiwan Semiconductor Manufacturing Company (TSMC), San Jose, CA USA

World s largest pure-play foundry company for contract semiconductor manufacturing

Manager (Test/Diagnosis)

Development of innovative solutions for yield ramp up and defect detection & diagnosis in 28/20nm

Development of complete test solutions for 2.5D/3D ICs and interface with EDA partners

Managing off-site test research and implementation team (Taiwan) for deployment of new methods

2009-2010 Duke University, Durham, NC USA

Host Prof. Krish Chakrabarty, Electrical & Computer Engineering Department

Visiting Researcher

Researched and managed SRC project on testing of small delay defects in advanced process nodes

2008-2009 LSI Corporation, Milpitas, CA USA

World s leader in storage and networking solutions

Principal Engineer

Developed new test and defect screening methods, and test cost reduction techniques

Developed roadmaps for future test challenges & evaluated their impact on company products

2007-2008 Magma Design Automation, San Jose, CA USA

World s leader in electronic design automation (EDA) and design tools

Member of Consulting Staff

Lead hardware compression and DFM-aware ATPG efforts for Magma ATPG tool

Participated in planning and support of new tool introduction in the EDA industry

2000-2007 Philips Research Laboratories, Eindhoven The Netherlands

One of the largest corporate research labs in the world

Senior Scientist

Researched new cost effective test methods/tools, test cost reduction techniques

Managed company-wide as well international standardization efforts for several key projects

Education

2005 Ph.D. in Electrical & Computer Engineering, University of Twente, Enschede,The Netherlands

Completed while working full time at Philips Research, Eindhoven

1998 1999 Masters in VLSI Design Tools and Technology, Indian Institute of Technology (IIT), Delhi, India

1994 1998 Bachelors in Electronics Engineering, Institute of Engineering and Technology (IET), Lucknow, India

Awards & Honours

IEEE International Test Conference 2010 most significant paper award

TSMC s outstanding procedure innovation award, Q3-2010

Finalist for the IEEE Test Technology Technical Counsel (TTTC) Best PhD Award 2005

ITC 00 paper selected in 40 most significant ITC papers ever

IEEE Senior member, 2005

Leadership Experience

Represented Philips in Accellera Open Compression Interface Standardization Committee

Representing TSMC in IEEE P1838 3D Test Working group

Topic chair/co-chair/session chair at Design Automation and Test in Europe (DATE 09, 2010, 2011)

Panellist and session chair at IEEE European Test Symposium (ETS 08)

Arrangement chair for the IEEE Silicon Debug and Diagnosis Workshop (SDD 07)

Organizer of panel session at ITC 09, ITC 08, ITC 06, and ETS 04

Organizer of IP track session at IEEE VLSI Test Symposium (VTS 05, and VTS 09)

Program committee member of various IEEE/ACM conferences: DATE (2009, 2010, 2011), ETS (2010,

2011), D3T (2009, 2010), RSDAT (2009, 2010), IIP (2004, 2005), DDECS (2006, 2007, 2008)

US/European Patents

Granted 1. Testing of circuits with plural clock domains (US7076709)

2. Test circuit and method for hierarchical core (US7380181)

3. Testing of an integrated circuit that contains secret Information (EP1915632)

4. Testing of an integrated circuit that contains secret Information (EP1917535)

5. Testing of circuits with plural clock domains (EP1472551)

6. Test circuit and method for hierarchical core (EP1787136)

7. Test prepared integrated circuit with an internal power supply domains (EP1875258)

Pending 8. Physical-aware testing of small delay defects (pending since 2010)

9. Test method and circuit for through-silicon-vias (pending since 2010)

10. Circuit and method for scan chain diagnosis (pending since 2011)

11. Test method and circuit for passive interposer testing (pending since 2011)

12. Probing techniques for high pin count devices (pending since 2011)

13. Method for generating test patterns for small delay defects (US20100153795)

14. Test circuit and method for testing of infant mortality related defects (US20100262876)

15. Method and an apparatus for evaluating small delay defect coverage (US20100262394)

16. Testing of an integrated circuit that contains secret Information (US20100264932)

17. Testable integrated circuit and IC test method (US20100231252)

18. Testing of an integrated circuit that contains secret Information (US20100223515)

Publications

Books 1. Sandeep Kumar Goel, Test-Access Planning and Test Scheduling for Embedded Core-Based System

Chip, Ph.D. thesis, University of Twente, The Netherlands, 2005, ISBN 90-74445-65-9.

2. Sandeep Kumar Goel and Krishnendu Chakrabarty, Testing for Small-Delay Defects in Nanoscale

CMOS Integrated Circuits, CRC Press, 2011

Book Chapters 3. Sandeep Kumar Goel and Krishnendu Chakrabarty, Power-Aware BIST and Test Data

Compression, Chapter 5 in Book "Power-Aware Testing and Test Strategies for Low Power

Devices", ISBN 978-1-4419-0927-5, Springer, New York, USA, 2009.

4. Sandeep Kumar Goel and Erik Jan Marinissen, On-Chip Test Infrastructure Design for Optimal

Multi-Site Testing Chapter 23 in Book System on Chip: Next Generation Electronics, ISBN: 0-86341-

552-0 & 978-086341-552-4, IEE Press, 2006.

5. Sandeep Kumar Goel and Erik Jan Marinissen, "Test Resource Management and Scheduling for

Modular Manufacturing Test of SOCs", Chapter 18 in Book Algorithms in Ambient Intelligence,

Volume 2, ISBN 978-1-4020-1757-5, Kluwer Academic Publishers, The Netherlands, 2004.

Journals 6. Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree,

Test Architecture Optimization and Test Scheduling for TSV-Based 3D Stacked ICs, submitted to

IEEE Transactions on Computer-Aided Design of ICs and Systems, 2011

7. Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, and Krishnendu Chakrabarty, Testing of

SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling,

IEEE Transactions on Computers, vol. 58, no. 3, pp. 409-423, March 2009

8. Sandeep Kumar Goel and Erik Jan Marinissen, Will Test Compression run out of Gas? Panel

summary, IEEE Design and Test of Computers, 2009

9. Sandeep Kumar Goel, Maurice Meijer, and Jose Pineda de Gyvez, Efficient Testing and Diagnosis of

Faulty Power Switches in SOCs, Proceedings IET Computers & Digital Techniques, vol. 1, issue 3,

pp. 230-236, May 2007

10. Erik Jan Marinissen and Sandeep Kumar Goel, Zero Defects: Mission Impossible ITC 2006 Panels,

IEEE Design and Test of Computers, vol. 24, no. 1, pp. 94-96 January 2007

11. Sandeep Kumar Goel and Erik Jan Marinissen, "Optimization of On-Chip Design-for-Test

Infrastructure for Maximal Multi-Site Test Throughput", Special issue Embedded Microelectronics

Systems: Status and Trends of IET Proceedings Computer and Digital Techniques, Vol. 152, Number

3, ISSN 1350-2387, June 2005

12. Sandeep Kumar Goel and Erik Jan Marinissen, "SOC Test Architecture Design for Efficient Utilization

of Test Bandwidth", In ACM Transactions on Design Automation of Electronic Systems (TODAES),

vol. 8, issue 4, pp. 399-429, October 2003

13. Sandeep Kumar Goel and Bart Vermeulen, "Data Invalidation Analysis for Scan-Based Debug on

Multiple-Clock System Chips", In Journals of Electronic Testing: Theory and Application (JETTA), vol.

19, issue 4, pp. 407-416, August 2003

14. Sandeep Kumar Goel and Erik Jan Marinissen, "A Test Time Reduction Algorithm for Test

Architecture Design for Core-Based System Chips", In Journals of Electronic Testing: Theory and

Application (JETTA), vol. 19, issue 4, pp. 425-435, August 2003

15. Bart Vermeulen and Sandeep Kumar Goel, "Design-for-Debug: Your Safety Net for Catching Design

Errors in Digital Chips", In IEEE Design and Test of Computers, Volume-2, May 2002

Conferences 16. Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, and Cheng Wen Wu, DfT Architecture

for 3D-SICs Having Multiple Towers, Accepted for IEEE European Test Symposium, 2011

17. Sandeep Kumar Goel, Gilbert Vandling, Charles Liu, Wei-pin Changchien, and Nan-Hsin Tseng, How

Real Are Small Delay Defects: A Silicon Case Study, submitted to IEEE International Test

Conference, 2011

18. Chun-Chuan Chi, Erik Jan Marinissen, and Sandeep Kumar Goel, Post-Bond Testing of 2.5D-SICs and

3D-SICs Containing a Passive Silicon Interposer Base, submitted to IEEE International Test

Conference, 2011

19. Sergej Deutsch, Vivek Chickermane, Brion Keller, Mario Konijnenburg, Erik Jan Marinissen, and

Sandeep Kumar Goel, Automation of 3D DfT Insertion and Interconnect Test Generation,

submitted to IEEE International Test Conference, 2011

20. Sandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng, and Mohammad

Tehranipoor, "Circuit Topology-Based Test Pattern Generation for Small Delay Defects, IEEE Asian

Test Symposium (ATS), 2010.

21. Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, and Jouke

Verbree, "Test-Architecture Optimization for TSV-Based 3D Stacked ICs, IEEE European Test

Symposium (ETS), 2010.

22. Sandeep Kumar Goel, Narendra Devta Prasanna, and Mark Ward, Comparing the Effectiveness of

Deterministic Bridge Fault and Multiple-Detect Stuck Fault Patterns for Physical Bridge Defects: A

Simulation and Silicon Study, IEEE International Test Conference (ITC), 2009

23. Narendra Devta Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, and Prabhu

Krishnamurthy, Accurate Measurement of Small Delay Defect Coverage of Test Patterns, IEEE

International Test Conference (ITC), 2009

24. Sandeep Kumar Goel, Narendra Devta Prasanna,and Ritesh Turakhia, Effective and Efficient Test

Pattern Generation for Small Delay Defects, IEEE VLSI Test Symposium (VTS), 2009

25. Ritesh Turakhia, Mark Ward, Sandeep Kumar Goel and Brady Benware, Bridging DFM Analysis and

Volume Diagnosis for Yield Learning, IEEE VLSI Test Symposium (VTS), 2009

26. Sandeep Kumar Goel and Erik Jan Marinissen, Will Test Compression Run Out of Gas? IEEE

International Test Conference (ITC), 2008

27. Sandeep Kumar Goel and Erik Jan Marinissen, Zero Defects: Mission Impossible, IEEE International

Test Conference (ITC), 2006

28. Harald Vranken, Sandeep Kumar Goel, Andreas Glowatz, Juergen Schloeffel, and Friedrich Hapke,

Fault Detection and Diagnosis with Parity Trees for Space Compaction of Test Respones .

ACM/IEEE Design Automation Conference (DAC 06), 2006

29. Sandeep Kumar Goel, Maurice Meijer, and Jose Pineda de Gyvez, Test and Diagnosis of Power

Switches in SOCs . IEEE European Test Symposium (ETS), 2006

30. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, and Krishnendu Chakrabarty, "Hierarchy-

Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips", IEEE/ACM Design

Automation and Test in Europe (DATE), 2006

31. Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, and Erik Jan Marinissen, "Test Scheduling for

Modular SOCs in an Abort-On-Fail Environment", IEEE European Test Symposium (ETS), 2005

32. Sandeep Kumar Goel and Erik Jan Marinissen, "On-Chip Test Infrastructure Design for Optimal

Multi-Site Testing of System Chips", IEEE/ACM Design Automation and Test in Europe (DATE), 2005

33. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, and Krishnendu Chakrabarty, "P1500-

Compliant Test Wrapper Design for Hierarchical Cores", IEEE International Test Conference (ITC),

2004

34. Sandeep Kumar Goel and Erik Jan Marinissen, "TR-Architect: DfT and Test Support for SOC

Designers", IEEE/ProRISC Workshop on Circuits, Systems, and Signal Processing (ProRISC), 2004

35. Bart Vermeulen, Zalfany Urfianto, and Sandeep Kumar Goel, "Automatic Generation of Breakpoint

Hardware for Silicon Debug", IEEE/ACM Design Automation Conference (DAC), 2004

36. Ludovic Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, and Bruno Rouzeyre,

"User-Constrained Test Architecture Design for Modular SOC Testing", IEEE European Test

Symposium (ETS), 2004

37. Sandeep Kumar Goel, "A Novel Wrapper Cell Design for Efficient Testing of Hierarchical Cores in

System Chips", IEEE European Test Symposium (ETS), 2004

38. Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, and Steven Oostdijk, "Test

Infrastructure Design for the Nexperia Home Platform PNX8550 System Chip", IEEE/ACM Design

Automation and Test in Europe (DATE), 2004

39. Sandeep Kumar Goel and Erik Jan Marinissen, "Control-Aware Test Architecture Design for Modular

SOC Testing", IEEE European Test Symposium (formally called European Test Workshop), 2003

40. Erik Jan Marinissen and Sandeep Kumar Goel, "SOC Test Infrastructure Optimization under Layout

Constraints", IEEE VLSI Test Symposium (VTS), 2003

41. Sandeep Kumar Goel and Erik Jan Marinissen, "Layout Driven Test Architecture Design of SOCs for

Test Time and Wire Length Minimization", Design Automation and Test in Europe (DATE), 2003

42. Sandeep Kumar Goel and Erik Jan Marinissen, "Test Resource Management and Scheduling for

Modular Manufacturing Test of SOCs", Philips Symposium on Intelligent Algorithms (SOIA), 2002

43. Sandeep Kumar Goel and Bart Vermeulen, "Hierarchical Data Invalidation Analysis for Scan-Based

Debug on Multiple-Clock System Chips", IEEE International Test Conference (ITC), 2002

44. Sandeep Kumar Goel and Erik Jan Marinissen, "Effective and Efficient Test Architecture Design for

SOCs", IEEE International Test Conference (ITC), 2002

45. Vikram Iyenger, Sandeep Kumar Goel, Erik Jan Marinissen, and Krishnendu Chakrabarty, "Test

Resource Optimization for Multisite Testing Using ATE With Memory Depth Constraints for SOCs",

IEEE International Test Conference (ITC), 2002

46. Bart Vermeulen, Tom Waayers, and Sandeep Kumar Goel, "Core-Based Scan Architecture for Silicon

Debug", IEEE International Test Conference (ITC), 2002

47. Sandeep Kumar Goel and Erik Jan Marinissen, "A Novel Test Time Reduction Algorithm for Test

Architecture Design for Core-Based System Chips", IEEE European Test Symposium, 2002

48. Sandeep Kumar Goel and Bart Vermeulen, "Data Invalidation Analysis for Scan-Based Debug on

Multiple-Clock System Chips", IEEE European Test Symposium, 2002

49. Erik Jan Marinissen and Sandeep Kumar Goel, "Analysis of Test Bandwidth Utilization in Test Bus

and TestRail Architectures for SOCs", IEEE Design and Diagnostics of Electronics Circuits and

Systems Workshop (DDECS), 2002

50. Sandeep Kumar Goel and Erik Jan Marinissen, "Cluster-Based Test Architecture Design for System-

on-Chip", IEEE VLSI Test Symposium (VTS), 2002

51. Bart Vermeulen, Gert Jan van Rootselar, and Sandeep Kumar Goel, "Debugging Systems on a Chip",

MEDEA Conference on Embedded System Design, 2000

52. Erik Jan Marinissen, Sandeep Kumar Goel, and Maurice Lousberg, "Wrapper Design for Embedded

Core Test", IEEE International Test Conference (ITC), 2000 (Selected as one of the most significant

papers in last 35 years of ITC).

Workshops 53. Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, and Cheng Wen Wu, DfT Architecture

for Multi-Tower 3D SICs, 3D Integration-Application, Technology, Architecture, Design Automation

and Test workshop at Design Automation and Test in Europe, 2011

54. Pengwei Ren, George Gaydadijev, AM Amory, M Lubaszewski, Erik Jan Marinissen, Kees Goossens,

Sandeep Kumar Goel, and F Moraes, Test Wrapper Design that Allows a Core to be Tested via a

NOC or Other Functional Interconnects, Diagnostic Services in Network-on-Chip Workshop at

Design Automation and Test in Europe, 2007

55. Sandeep Kumar Goel and Erik Jan Marinissen, "Test Infrastructure Design for High-Throughput

Multi-Site Testing of System Chips", IEEE Infrastructure IP Workshop (I-IP), 2004

56. Zalfany Urfianto, Sandeep Kumar Goel, and Bart Vermeulen, "Automatic Generation of Breakpoint

Hardware for Silicon Debug", IEEE Infrastructure IP Workshop (I-IP), 2003

57. Vikram Iyenger, Sandeep Kumar Goel, Erik Jan Marinissen, and Krishnendu Chakrabarty, "On SOC

Test Resource Optimization for Multisite Testing Using ATE With Memory Depth Constraints", IEEE

North Atlantic Test Workshop (NATW), 2002

58. Vikram Iyenger, Sandeep Kumar Goel, Erik Jan Marinissen, and Krishnendu Chakrabarty, "On SOC

Test Resource Optimization for Multisite Testing Using ATE With Memory Depth Constraints", IEEE

European Test Workshop (ETW), 2002

59. Sandeep Kumar Goel and Erik Jan Marinissen, "TAM Architectures and Their Implications on Test

Application Time", IEEE International Workshop on Testing of Core-Based System Chips (TECS), 2001

Panels/ 60. Sandeep Kumar Goel and Erik Jan Marinissen, Testing of 3D Chips: Is There Anything New Under

Presentations the Sun? Panel sesion, IEEE International Test Conference (ITC), 2009

61. Narendra Devta Prasanna and Sandeep Kumar Goel, "Test Pattern Generation Methods for Small

Delay Defect Testing", Presentation at Mentor Graphics s User2User Conference, 2009

62. Sandeep Kumar Goel and Mark Ward, Value of DFM in volume diagnosis arena, IP session at IEEE

VLSI Test Symposium (VTS), 2009

63. Sandeep Kumar Goel and Erik Jan Marinissen, Will Test Compression Run Out of Gas? Panel session,

IEEE International Test Conference (ITC), 2008

64. Sandeep Kumar Goel, Geir Eide and Robert J. Thompson, Physical-Aware ATPG: What Does It

Really Mean?, Presentation at IEEE European Test Symposium (ETS), 2008

65. Sandeep Kumar Goel, Panelist at panel Commercial Tools for RTL DFT Exist? But How Good Are

They?, IEEE European Test Symposium (ETS), 2008

66. Sandeep Kumar Goel and Erik Jan Marinissen, Zero Defects: Mission Impossible, Panel Session at

IEEE International Test Conference (ITC), Oct 2006

67. Sandeep Kumar Goel, The VLSI Seminar Series, Computer Engineering Research Center, University

of Texas at Austin, Texas, 2005 (Invited by Prof. Nur Touba, Electrical and Computer Engineering

Dept.)

68. Sandeep Kumar Goel, "Multi-Site Test", IP Session at IEEE VLSI Test Symposium (VTS), 2005

69. Sandeep Kumar Goel, Duke University, Durham, 2004 (Invited by Prof. Krishnendu Chakrabarty,

Electrical and Computer Engineering Dept.)

70. Sandeep Kumar Goel and Erik Jan Marinissen, "Reducing Test Cost: How Much Multi-Site Can You

Handle?" Panel Session at IEEE European Test Symposium (ETS), 2004

Invited Lectures

Duke University, Durham, NC, USA, November 2004 (Invited by Prof. Krish Chakrabarty)

University of Texas at Austin, Texas, USA., November, 2005 (Invited by Prof. Nur Touba)

Philips Center for Technical Training (CTT), Low-cost Testing, November, 2006, The Netherlands

References

Available on request

Contact this candidate