Design Test
Resume:
Nick Atchison
Email: *********@********.***
Address: *** ******** **.
City: Boulder Creek
State: MT
Zip: 59006
Country: USA
Phone: 831-***-****
Skill Level: Director
Salary Range: $200,000
Willing to Relocate
Primary Skills/Experience:
See Resume
Educational Background:
See Resume
Job History / Details:
150 Lanktree Ln.
Boulder Creek, CA 95006
(C) 831-***-****
E-Mail: *********@********.***
dlxplx.com Demo of Integrated Yield Management Software.
holomirage.com. Demo of New Produce Introduction Simulator.
OBJECTIVE
Sr. Staff NPI/Device Engineer: Responsible for all aspects of New Device Design and New Product Implementation. This includes planning, class -S- documentation, W2T simulation, test structure design, test structure test, experimental design, tooling design, foundry contracts, product characterization, product qualification, MCM package design, package qualification, electrical failure analysis, physical failure analysis, cost analysis and engineering production scheduling.
CAPABILITY SUMMARY:
CORPORATE MANAGEMENT ASSISTANCE
AUTOMATION TOOLS
* State of the art -Computer Aided Manufacturing- software
* State of the art -Integrated Yield Management- software
* State of the art -Computer Aided Project Management- software
* Integrated Project Data Base to store memos, documentation and data.
* Generation of patents and patent applications
* Systems that automatically convert Product Data Sheets into a complete startup plan with On-Line documentation, training reporting.
DOCUMENTATION
* Generation of forms for PO`s, BOM`s. small tooling and netlists.
* WEB tool to guide customers to promotional articles.
* Patent formlulation
TRAINING
* Set up specifications on SBC based WEB server using HTML/PDF format.
* WEB based training schedule and monitor for each employee.
FINANCE
* Project schedule with staffing, cost accounting and report system
MARKETING
* Engineering data sheet with all information related to a product.
* Marketing/production ramp, cost, price and competition schedule.
* Attend meeting and seminars with marketing team as technical support.
TECHNICAL OPERATIONS ASSISTANCE
DEVICE
* Evaluate available technologies and devices.
* Develop new semiconductor technologies and devices.
* Extend performance of existing technologies and devices.
* Maximize performance of fabrication technology.
* Develop needed e-test structures, test programs and analysis programs.
* Perform device characterization and modeling in support of IC design.
* Develop foundry wafer acceptance structures, procedures.
* Develop and verify measurements via statistical process control.
* Perform continuous improvement of device performance metrics.
* Statistical data analysis program development and automation.
* Device physics for Bipolar, MOS SiG technologies.
* E-test structure and product die stress testing methods.
* E-test, wafer probe and package test automated root cause analysis
* Off shore foundry management.
* Transfer and ramp to high volume production advanced technologies.
* Provide direction and support for international foundries.
* Foundry e-test, test programs and analysis programs.
* Foundry wafer acceptance structures, procedures and measurements.
* Maximize performance of foundry fabrication technology.
* Assist Product Engineering to resolve foundry yield and reliability
* Feedback to foundry partners on device parametric performance
* Coordinate failure analysis activities with foundry for parametric failures.
* Document results using advances web based data base systems.
* JTAG verification tools
PACKAGE
* Expert at wafer scale, stacked die and MCM packaging
* Package development and netlist verification tools.
* Stacked Die and die MCM package development.
* Wafer Scale Package Development tools - Simplex EVOP
* Back lap, back grind and backside chemical etch deconstruction tools for stacked die MCM packages.
DESIGN
* Contribute to design engineering at all levels,
* Measurement and modeling validation.
* Coordinate modeling activities and design kit generation Kit parts
* Assist design verification using CPLD, Gate Array & Silicon Express.
* Perform device characterization and modeling on test run parts.
* Sart burn in as soon as possible with kit parts.
* Design for test, EFA, PFA, Redundancy, modularity and enhanced JTAG.
* Develop all needed e-test structures, test programs and analysis program
MANUFACTURING ENGINEERING ASSISTANCE
* WAFER FOUNDRY
* International multilingual foundry phone meetings.
* Manage the set-up of foundries on and off shore.
* Site evaluation of available foundry technologies,
* Provide technical expertise and foundry process support.
* Responsible for foundry performance to statistical standards.
ASSEMBLY
* Same AS Wafer Foundry.
PRODUCT
* Sun, PC & SBC based servers to act as Product Engineering Simulators.
* Product characterization systems with only 5 wafers.
* Program an automated device failure root cause analysis system/
* Adjust foundry schedules
* Verify PO`s and C of C`s
* Supervise the FAB equipment parameter to e-test device parameter, e-test parameter to wafer sort parameter and wafer sort parameter to reliability parameter using the automated IYM Yeild Analysis System.
TEST
* Automated Test Generation
* Automated Test Verification
* Automated New Stress Test Development
* Automated Test Performance Reporting
* Tester Selection.
RELAIBILITY
* Responsible for determining and fixing root-causes of Fab line and parametric test yield loss & line yield loss.
* Responsible for determining and fixing root-causes of wafer sort and package test yield loss.
* Responsible for determining and fixing root-causes of reliability failures and customer returns.
* Able to evaluate changes and put permanent solutions in place.
* Responsible for maximizing process capability (Cpks) for both in-line process and parametric testing critical parameters
* Responsible for optimizing the process flows with a goal to simplify manufacturing and to reduce cost.
* Proven ability to develop and manage web based documentation systems.
* Working knowledge of applied statistics (SPC/DOE).
* Electrical and physical reliability measurements.
* Develop new failure analysis methods and techniques as needed.
* Develop the qualification plan
* Hands on root cause analysis using E-test, Test, Physical Deconstruction and exploratory Stress testing.
* Design specialty optoelectronic tooling, equipment and testers as needed.
* Maintain automated SPC repor
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