Engineer Assistant

Lin Ma

website: http://www.cse.wustl.edu/~lin.ma/ email: ***.**@***.*****.***

Research Interest Parallel Architecture and Algorithms, Hybrid Computing Engines Consist of CPU and GPU, Per-

formance Evaluation and Tuning Model for Multi-threading System, Accelerating Application-

Speci c Architectures (Networking, Computational Finance and Computational Bioinformatics)

2008 - Present

Education Washington University in Saint Louis

PhD Candidate in Computer Science Advisor: Prof. Roger Chamberlain

2005 - 2008

Beijing University of Posts and Telecommunications

Master of Science in Computer Science First Class with Distinction

Research Assistant

Professional Laboratory of Storage Based Supercomputing

August 2008 - Present

Saint Louis, MO

Experience

-Accelerate sequence similarity search tool BLASTN by implementing parallel Bloom Filters on

GPU. Design analytic performance model that helps potential users of Bloom lters to quantify

the inherent tradeo s between throughput and false positive rates. Optimized reduction of GPU

dynamic con guration space (usage of threads, blocks, shared memory and registers) is also

investigated to guarrantee peak throughput. Over 5k lines of CUDA codes.

-Design a sysnthetic micro-bencmark that helps improve the understanding of the performance of

memory-limited kernels, especially as impacted by caches and various con guration parameters

that can be used to tune kernel execution. Based on that, an analytical model is proposed and

explored, which is then followed by an empirical validation using a pair of production applications

used in computational biology(DNA Classi cation and BLAST). Over 5k lines of CUDA codes.

-Partition computationally intensive Monte Carlo Simulation of Finance Model into sets of tasks

and e ciently map across computation nodes throughout a streaming pipeline. Speed up archi-

tecturally diverse system by exploring data transfer between interfaces of CPU, GPU & FPGA.

Teaching Assistant

Machine Learning Group, WUSTL

2010 Fall Semester

Saint Louis, MO

Served as TA of class Arti cial Intelligence, leading recitation each week regarding theoretical

assignments, and running project tutorials about the programming assignments.

Architecture Engineer Intern

Intel Corporation

2007 - Summer 2008

Beijing, China

Helped design and deploy WiMAX Network and Application Model for 2008 Olympic Sailing.

Student Research Assistant

National Key Laboratory of Networking and Switching

Summer 2005 - Spring 2008

Beijing, China

Focused on IP and Broadband Networking and Management(wired&wireless). Closely cooper-

ated with China Mobile Co. Ltd., Lucent, Ericsson, Notel, etc., drafted several National Network

Management Standards that o cially stipulated for industry companies to follow in China.

Software R&D Engineer Intern

MetarNet Co.Ltd.

Summer 2007

Beijing, China

Developed GUI and interface with backend modules of Network Management System that covers

a large number of telecommunication cells and links throughout 18 provinces topology in China.

Publications

1. L. Ma, R. D. Chamberlain, A Performance Model for Memory Bandwidth Constrained Ap-

plications on Graphics Engines, Proceedings of IEEE ASAP, July 2012.

2. L. Ma, R. D. Chamberlain, J. D. Buhler, M. A. Franklin. Bloom Filter Performance on

Graphics Engines, Proceedings of IEEE ICPP, Sep 2011.

3. Technical Report: GPU Memory Performance Test Report, 2010.

4. L. Ma, L. Rui, An End-to-end QoS Frame for Multimedia Provision in Tight-coupled Inter-

working of WiMAX and IMS, IEEE ICNSC, Apr 2008.

5. L. Ma, M. Zhao, J. Yan. Borrow Time from Future, MCM. USA, Feb 2004 (Awarded Paper).

Services &

1. NVIDIA s CUDA Developer Program, Mar 2011.

Awards

2. Reviewer for IEEE IPDPS 2012

3. IEEE ASAP Student Travel Grant, Aug 2009

4. Outstanding Graduate in Beijing University of Posts and Telecoms, 2008

3rd Place Award in International MCM : The Mathematical Contest in Modeling, Feb 2002

5.

4 Times 1st Prize National Scholarship, 2001-2005

6.

Skills Programming Languages:

C, C++, Python, Java, Shells, R, Cilk

Framework and Tools:

NVIDIA CUDA, CUDA-GDB, CUDA Pro ler, Matlab, Emacs, Linux, ModelSim, L TEX

A

Language:

Fluent English, Native Chinese, with excellent communication and troubleshooting ability

Core Courses:

Advanced Data Structures and Algorithms

Computer System Architecture

Operating System Organization

Translation of Computer Languages

Arti cial Intelligence

Parallel Algorithms and Architectures

Statistical Computing for Scienti c Research

Protocols for Computer Networks

Wireless Networking

Course Projects Processing Unit Design:

Designed and implemented in VHDL a simple CPU with 32-bit instruction set, multi-threading

switch, and central controlled 5-stages pipeline. RAW, branch hazard and cache miss are well

handled. A couple of testing modules were setup to ensure correctness

Parallel SAT-Solver:

Designed and implemented a simple Parallel SAT-Solver on GPU using CSP algorithms and

search system: BFS, DFS. Memory locality was also taken into considered in terms of GPU

global memory and shared memory.

Compiler:

Designed and implemented a workable compiler for translating source code from a high-level

programming language to assembly language. It can render lexical analysis, parsing, semantic

analysis, and code generation.

Operating System Shell:

Designed a command-line shell which implements functions of parsing arguments, setting de-

bug levels, searching paths, ful lling several built-in commands, substituting variables, redirect-

ing stdin/stdout, background commands, pipelines, and terminal-generated signals(SIGINT). A

thread library which supports concurrent execution and preemptive scheduling of threads was

also implemented.

Dynamic Task Planner:

Designed and implemented a GUI-friendly calendar with function of dynamically planning tasks

so as to get the minimum con icting constraints. PDDL 3.0 and MiniSat Solver were utilized in

this tool for handling tasks with preferences.

Contact this candidate