Pablo Montesinos

University of Illinois at Urbana-Champaign abphf8@r.postjobfree.com

http://iacoma.cs.uiuc.edu/ pmontesi/

Department of Computer Science

*** *. ******* ***.

Urbana, IL, 61801-2302

Tel. 217-***-**** (O ce)

Tel. 217-***-**** (Cell)

Multicore and parallel computer architecture. Deterministic replay of parallel execution.

Research

Programmability of parallel architectures. Architecture support for debugging and program

Interests

development. Interface between architecture and operating systems.

Education University of Illinois at Urbana-Champaign (UIUC), Urbana, IL

Ph.D. in Computer Science, June 2009 (expected)

Advisor: Josep Torrellas

Thesis: Practical Deterministic Replay Of Multiprocessor Systems

University of Illinois at Urbana-Champaign (UIUC), Urbana, IL

M.S. in Computer Science, December 2005

Universidad de Le n, Spain

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B.S. in Computer Engineering, October 2001

Awards and W. J. Poppelbaum Award - 2009

Awarded by the UIUC Computer Science Department to a graduate student in computer

Honors

architecture, based on academic merit and creativity.

Selected for a Research Highlight in Communications of the ACM for DeLorean:

Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution E -

ciently, 2008

La Caixa Fellowship - 2003-2005

This program supports the best Spanish graduate students to study abroad.

Valedictorian Award, Universidad de Le n - 2001

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Education and Science Ministry of Spain, Research Fellowship - 2000-2001

Department of Mathematics, Universidad de Le n, Research Fellowship - 2000

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National Champion and European Finalist - 1997

European Competition for Educational Multimedia Software.

Regional Math Olympics Winner. National nalist - 1997.

Publications Deterministic Replay And Multiprocessor Architecture

1. Josep Torrellas, Luis Ceze, James Tuck, C lin Ca caval, Pablo Montesinos, Wonsun Ahn

a s

and Milos Prvulovic, The Bulk Multicore Architecture for Improved Programmability . To

Appear in Communications of the ACM, December 2009.

2. Pablo Montesinos, Matthew Hicks, Samuel T. King and Josep Torrellas, Capo: Abstrac-

tions and Software-Hardware Interface for Hardware-Assisted Deterministic Multiprocessor

Replay, 14th International Conference on Architectural Support for Programming Lan-

guages and Operating Systems (ASPLOS), March 2009.

Curriculum Vitae Pablo Montesinos

3. Derek R. Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill and Josep Torrellas, De-

terministic Replay of Multiprocessor Programs, Communications of the ACM (CACM), to

appear, 2009.

4. Pablo Montesinos, Luis Ceze and Josep Torrellas, DeLorean: Recording and Determinis-

tically Replaying Shared-Memory Multiprocessor Execution E ciently, 33th Annual Inter-

national Symposium on Computer Architecture (ISCA), Pages: 289-300, June 2008.

5. Luis Ceze, James Tuck, Pablo Montesinos and Josep Torrellas, Bulk Enforcement of

Sequential Consistency, 34th Annual International Symposium on Computer Architecture

(ISCA), Pages: 278-289, June 2007.

6. Luis Ceze, Pablo Montesinos, Christoph von Praun, and Josep Torrellas, Colorama:

Architectural Support for Data-Centric Synchronization, 13th International Symposium on

High-Performance Computer Architecture (HPCA), Pages: 133-144. February 2007

Multiprocessor Programmability

7. Luis Ceze, Christoph von Praun, C lin Ca caval, Pablo Montesinos, and Josep Torrellas,

a s

Programming and Debugging Shared Memory Programs with Data Coloring, Workshop on

Compilers for Parallel Computing (CPC), January 2009

8. Luis Ceze, Christoph von Praun, C lin Ca caval, Pablo Montesinos, and Josep Torrellas,

a s

Concurrency Control with Data Coloring, Workshop on Memory Systems Performance

and Correctness (MSPC), March 2008

Processor and System Reliability

9. Pablo Montesinos, Wei Liu, and Josep Torrellas, Using Register Lifetime Predictions To

Protect Register Files Against Soft Errors, Extended version of [10]. Invited Paper to the

IEEE Transactions on Dependable and Secure Computing, (IEEE TDSC), to appear, 2009

10. Pablo Montesinos, Wei Liu, and Josep Torrellas, Using Register Lifetime Predictions to

Protect Register Files Against Soft Errors, 37th International Conference on Dependable

System and Networks (DSN). Pages 286-296. June 2007

11. Pablo Montesinos, Wei Liu, and Josep Torrellas, Shield: Cost-E ective Soft-Error Pro-

tection for Register Files, Third IBM TJ Watson Conference on Interaction between Archi-

tecture, Circuits and Compilers (PAC2 ), October 2006

12. Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, and Josep Torrellas, ReViveI/O:

E cient Handling of I/O in Highly-Available Rollback-Recovery Servers, 12th International

Symposium on High-Performance Computer Architecture (HPCA), Pages: 203-214. Febru-

ary 2006

Other Papers and Software

13. Pablo Montesinos, Stage Driver, 12th Conference on Pattern Languages of Programs

(PLoP). June 2005

14. Jose Renau, Basilio Fraguela, James Tuck, Wei Liu, Milos Prvulovic, Luis Ceze, Smruti

Sarangi, Paul Sack, Karin Strauss and Pablo Montesinos. SESC Simulator,

http://sesc.sourceforge.net. 2005

Curriculum Vitae Pablo Montesinos

Papers Under Review

15. Pablo Montesinos, Matthew D. Hicks, Wonsun Ahn, Samuel T. King and Josep Torrel-

las, Lessons Learned During the Development of the CapoOne Deterministic Multiprocessor

Replay System . Submitted for publication. 2009.

Master Thesis: Shield: Resource-E cient Protection for Register Files, UIUC. May 2005.

Theses

Advisor: Josep Torrellas

B.S. Diploma Thesis: Compressed File Systems, Universidad de Le n. September 2001.

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Advisor: Araceli de Francisco

Research Graduate Research Assistant, i-acoma group, UIUC.

2003-present.

Experience

Advisor: Josep Torrellas.

I work in the Intel-Microsoft Universal Parallel Computer Research Center (UPCRC) at the

University of Illinois. My research has focused on hardware and software support for multipro-

cessor architectures. A major emphasis has been e ective deterministic replay of multicore

systems. Speci cally, I proposed Capo (ASPLOS 09), the rst software-hardware interface

for practical hardware-assisted deterministic replay of shared-memory multiprocessors, and

developed CapoOne, its rst implementation. High-performance multiprocessor replay needs

a system that can e ciently record the interleaving of memory operations. Thus, I proposed

and evaluated DeLorean (ISCA 08, CACM 09), a new hardware architecture for high-speed

deterministic replay based on chunk execution (ISCA 07).

Another area I have worked on is improving the programmability of multiprocessors, in-

cluding a novel architecture (HPCA 07) and programming models for hardware-based data

centric synchronization (CPC 09, MSPC 08, HPCA 07).

Finally, I have also worked on reliability, at both processor and system level. At the pro-

cessor level, I proposed Shield (IEEE TDSC 09,DSN 07, PAC2 06), an e cient register- le

protection mechanism where registers are only protected while they contain useful data. At

the system level, I have helped implement and evaluate ReVive I/O, a scheme that enables

I/O undo/redo in architectures with high-frequency checkpointing (HPCA 06).

Graduate Research Intern, Intel Corporation. Oregon.

Summer 2006.

Mentor: Scott Hahn.

I evaluated and optimized virtualization environments for manycore architectures.

Research Intern, Universidad de Le n. o

2000-2001

Advisor: Araceli de Francisco Iribarren.

I developed and evaluated a kernel driver for the BeOS operating system that was able to

read, write and mount compressed volumes.

Teaching Assistant, Parallel Computer Architectures. UIUC.

Teaching

Spring 2006 and Spring 2008.

Experience

Advanced graduate-level course with 30 students. Topics included research issues in parallel

architectures. Responsibilities included assigning and grading homeworks and class projects,

as well as holding o ce hours. I also gave multiple lectures.

Curriculum Vitae Pablo Montesinos

Lecturer, Introduction to Operating Systems. Universidad de Le n.

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February 2003 - August 2003.

Undergraduate level course with 100 students. Topics included basic concepts on operating

systems. Responsibilities included lecturing two times per week, assigning and grading home-

works, machine problems and exams, as well as holding o ce hours.

Lecturer, Operating System Design. Universidad de Le n.

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February 2003 - August 2003.

Undergraduate level course with 15 students. Topics included operating systems architecture.

Responsibilities included lecturing two times per week, assigning and grading homeworks, ma-

chine problems and exams, as well as holding o ce hours.

Capo: Abstractions and Software-Hardware Interface for Hardware-Assisted Deterministic

Multiprocessor Replay, 14th International Conference on Architectural Support for Program-

Talks

ming Languages and Operating Systems (ASPLOS), March 2009.

E cient Recording and Deterministic Replay of Shared-Memory Multiprocessor Programs.

Intel-Microsoft Universal Parallel Computing Research Center at the University of Illinois.

December 2008.

E cient Recording and Deterministic Replay of Shared-Memory Multiprocessors. Intel Corp.

Hillsboro, Oregon. October 2008.

Recording and Deterministically Replaying Shared Memory Multiprocessor Execution E -

ciently, 35th Annual International Symposium on Computer Architecture (ISCA), Beijing,

China, June 2008.

Chunk-Based Execution and Deterministic Replay. Invited talk. Guest speaker at the Depar-

tamento de Ingenier El ctrica y Electr nica, Universidad de Le n. Spain, May 2008.

a e o o

Concurrency Control with Data Coloring, Workshop on Memory Systems Performance and

Correctness, Seattle, March 2008

Using Register Lifetime Predictions to Protect Register Files Against Soft Errors, 37th In-

ternational Conference on Dependable System and Networks (DSN), Edinburgh, Scotland.

June 2007.

Shield: Cost-E ective Soft-Error Protection for Register Files, Third IBM TJ Watson Con-

ference on Interaction between Architecture (PAC2 ), Yorktown Heights, NY. October 2006.

ReViveI/O: E cient Handling of I/O in Highly-Available Rollback-Recover y Servers, 12th

International Symposium on High-Performance Computer Architecture (HPCA), Austin,

Texas. February 2006.

Junior R&D Developer, Ydilo Advanced Voice Solutions. Madrid, Spain. June 2002 -

Industry

December 2002. Design and development of voice applications based on Java, C++, Oracle

Experience

and NUANCE systems.

Organized seminar in UIUC research group (2006-2007).

Service

Reviewer for ASPLOS, DSN, HPCA, ISCA, MICRO, IEEE Transactions on Computers.

Student Member of IEEE and ACM.

President and Secretary of Unicyber, a student organization at the Universidad de Le n.

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References Pablo Montesinos

References Prof. Josep Torrellas.

Advisor, Dissertation chair.

Department of Computer Science, UIUC.

abphf8@r.postjobfree.com

Prof. Samuel T. King.

Co-Advisor. Dissertation committee member.

Department of Computer Science, UIUC.

abphf8@r.postjobfree.com

Prof. Marc Snir.

Dissertation committee member.

Department of Computer Science, UIUC.

abphf8@r.postjobfree.com

Prof. Wen-mei W. Hwu.

Dissertation committee member.

Electrical and Computer Engineering, UIUC.

abphf8@r.postjobfree.com

Prof. Yuanyuan Zhou.

Dissertation committee member.

Department of Computer Science, UIUC.

abphf8@r.postjobfree.com

Prof. Christoph von Praun.

Dissertation committee member.

Georg-Simon-Ohm University, Department of Computer Science. Nuremberg, Germany.

abphf8@r.postjobfree.com

Scott Hahn.

Intel Mentor.

Intel Labs, Hillsboro, Oregon.

abphf8@r.postjobfree.com

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