Design Software Engineer

Vinit S. Apte

**** ******** **,*******,**:***** M: 919-***-**** mailto: abpavz@r.postjobfree.com

OBJECTIVE:

Seeking a full time position in the field of ASIC Design/Verification, Computer Architecture, VLSI.

EDUCATION:

Master of Science in Computer Engineering,(May 2012 expected) GPA: 3.4

North Carolina State University Raleigh NC USA

Relevant Coursework:Computer Design and Technology, ASIC Design, VLSI System Design,

Architecture of Parallel Computers, Computer Networks, DSP.

Fall 2011 Courses: ASIC Verification, Embedded Systems with Linux and Android, Managing Complex

IT Systems

Bachelor of Engineering in Electronics, GPA: 3.65

Vishwakarma Institute of Technology, University of Pune, India

PROFESSIONAL EXPERIENCE:

December 2009-June 2010: Associate Software Engineer, Accenture Services Pvt. Ltd.

TECHNICAL SKILLS:

Languages: C, C++, Verilog, System Verilog, Perl, 8051/8085 Assembly Language Programming,

VHDL, OpenMP.

Operating Systems: Linux, Windows.

Tools: HSpice, Modelsim, Synopsys Design Vision, Cadence Tool Suite (Virtuoso Schematic Editor,

Virtuoso Layout Editor),Matlab, AVR Studio, Analog Artist.

PROJECTS:

COMPUTER ARCHITECTURE/CPU ARCHITECTURE

1) CACHE DESIGN, MEMORY HIERARCHY DESIGN: Designed a generic cache module

that can be used at any level of memory hierarchy. The cache was configurable in terms of

supporting any cache size, associativity and block size. Evaluated the simulator with

SPEC address traces for gcc, perl,vortex, compress and go. Analyzed the trends in

Miss Rates, Average Access Time (AAT), Energy Delay Product (EDP) for multiple

configurations using PERL scripting.

2) BRANCH PREDICTOR: Designed a Brach Predictor that was configurable in terms of

supporting any prediction algorithm such as Bimodal, G-share and Hybrid. Evaluated the

simulator using SPEC address traces and analyzed the trends such as Number of

Mispredictions and Misprediction-Rate.

3) TOMOSOLA S OUT OF ORDER EXECUTION PIPELINE: Implemented Tomasulo s out

of order execution pipeline for microprocessors in form of simulator and measuring the

performance for different scalar and superscalar designs in C.

VLSI DESIGN

1) Designed and simulated high speed 45nm, 64bit Content Addressable Memory (CAM)

working at 1Ghz using Virtuoso Schematic and Layout Editor and performed the LVS and

the DRC checks for the same. It had a 9T NOR type bitcell, Dynamic Decoder, Bit

Line/Search-Line conditioning circuitry, Priority Encoder(Low), TSPC Registers.

ASIC DESIGN/VERIFICATION

1) Designed and implemented Viterbi Decoder that solves the Hidden Markov Model Problem

using ModelSim for RTL and did Synthesis for the same using Synopsys Design Vision.

Calculated the Area, Energy, Delay and generated Timing reports using the TCL scripts.

2) Designed a layered test bench capable of generating multiple constrained and

randomized instructions and an interface to the DUT to verify various functionalities

of a Basic ALU.

3) Designed and Synthesized a search engine where two string searches happen in

parallel using Verilog HDL. The two strings to be searched were stored in the

memory using memory generators.

4) Designed, Synthesized and Verified a module that accumulated statistics on an

incoming data stream consisting of two individual bytes in Verilog HDL. The

statistics accumulated were in terms Grey Code or Even Parity observed in individual

bytes.

5) Currently working on Verification of PIPELINED LC -3 Microcontroller with a

comprehensive instruction set. The aim is to verify data and control path of LC-3 with

System Verilog using a Layered and Object Oriented Testbench.

EMBEDDED SYSTEMS

1) Developed an application for an ARM microprocessor on a Beagleboard for

calculating the distance from an arbitrary position on the surface of the earth to the

nearest monitoring station and evaluated the timing behavior for the same.

2) Performed the Analysis and Optimization of a JPEG Image Decompression. Gprof

and Oprof were used to gather timing information which was used alongwith

Advanced SIMD instructions in optimizing the code.

PARALLEL PROGRAMMING

1) Cache Coherence Protocols Simulator (MSI/MESI/MOESI) implementation in C++.

Analyzed the speed up obtained with respect to the different number of threads.

2) Open MP Parallel Programming: Parallelization of Diagonalization loop in Gauss Law,

Parallelization of loop in Image Processing, Single/Doubly Link list Paralle lization with

implementation of user defined locks.

PAPER PRESENTATIONS AND PUBLICATIONS:

Presented a paper on Machine Vision at VITALITY 2009 which was a technical event held a t

Vishwakarma Institute of Technology,Pune.

Presented a paper on Stereo Vision and Applications at Credenz 2008 which was a technical

event held at Pune Institute of Computer Technology,Pune.

http://www.eeweb.com/project/vinit_apte/depth-perception-using-stereo-vision

AWARDS APPRECIATIONS AND ACHIEVEMENTS:

Ranked ninth in University of Pune examination for year 2007-08.

Successfully completed Accenture s Greenfield Training in SAP-ABAP.

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