Engineer Design
Resume:
Amar Vattakandy
Asic Design / Design Verification Engineer
1023
Sparrow Hawk Dr.
Longmont,
CO 80501 ****.**********@*****.***
Summary
A hardware engineer with over twelve yearsof
experience in all phases of the chip development process. Expertise
includes Architecture, Logic and System design, Design Verification
and Post Silicon Verification. Currently seeking a position as a technical
contributor where my skills and experience would add value to the company.
Skills
Hardware
Software
Verilog, VHDL, SystemVerilog, Specman E
VLSI,ASIC,FPGA,CPLD Design Methodology
Complex Design Verification Environment Design.
X86 Silicon and System Architecture
PC Architecture and Legacy Issues
PC Bus Protocols (Pentium, P6, HyperTransport, PCI,
ISA, EDO/SDRAM/DDR)
Synopsys Design Compiler, Physical Compiler, IC
Compiler, PrimeTime, PowerCompiler, DFTCompiler, Cadence LEC
C,C++,Java
Perl, Python, Tcl
x86 Assembly Language (MASM,GAS)
Linux Kernel/Drivers
GUI programming (GTk, PerlTk, Tkinter)
Javascript,PHP,SQL
Work History
Advanced Micro Devices (AMD): Member, Technical Staff
(8/2003 - Present)
90nm Test-Chip Architecture and Design:
Architected a test chip for validating the 90nm design
flow, involving a mix of digital and analog circuit blocks.
Designed an at-speed path-delay testing infrastructure
using internal PLLs.
Took this architecture through the entire silicon flow
including the design, functional verification, synthesis, scan insertion, gate level
simulation, formal verification, pre-tape-out timing fixes and post silicon
verification.
Advanced Programmable Interrupt Controller (APIC)
Functional Verification:
Created a directed random test framework for CPU
interrupt testing using high-level tests written in C.
Drove architectural decisions involved in the adoption
of multi-core AMD APIC subsystem to the single-core Geode product line.
Floating Point Unit (FPU) Functional Verification:
Created a Linux based 2nd-generation perpetual random
verification framework that generates FPU stimuli using networked machines and
verifies correct operation on the design database.
Worked on the implementation of an algorithm that
generated hard-to-round divide input pairs.
Floating Point Unit Design Maintenance:
Main contact for analyzing Geode FPU functional
anomalies.
Implemented ECOs and functional modifications to fix
issues in the FPU design.
CPU Debug Hardware Design:
Created a hardware debugger using the JTAG port on the
Geode processors.
Wrote a parallel port Linux driver for the above
hardware.
Wrote a Python based command line interface for this
debugger.
Post-Silicon Random Testing Framework:
Designed and maintained an infrastructure that executes
random x86 instruction streams on real silicon.
National
Semiconductor Corporation: Member, Technical Staff (1/1998 - 8/2003)
Level 2 Cache Controller Design:
Designed a 128KB 4-way Victim L2 Cache Controller for
the Geode Processors.
Implemented a novel replacement scheme that reduced
accesses to the main memory.
The L2 cache improved the performance of the CPU by a
maximum of 15%.
Floating Point Unit (FPU) Functional Verification:
Created a randomizable environment for block level
verification of the FPU.
Worked on proving the accuracy of reciprocal and square
root implementations using hard-to-round inputs.
Wrote the floating-point module of the internal x86
processor software emulator used in higher level functional verification.
Designed an infrastructure to track out-of-order
execution status of the FPU to validate instruction stream accuracy.
Architected a random test environment to assert
pre-silicon design accuracy using an actual external FPU.
Display Controller/Accelerator Verification:
Created a random stimulus generator for the integrated
2D graphics accelerator.
Wrote a constrained random verification environment for
the display controller.
CPU core and peripherals Debug:
Debug of complex system level problems and software
issues.
A custom debug methodology of using System Management
Interrupts to report system state is employed in these efforts.
System Level Test Hardware Design:
Designed a CPLD based programmable ISA Interrupt
Generator.
Designed a CPLD based PCI Port X card.
Architected a 16MB linear PCI flash array for diskless
booting.
Opti Inc: Senior Application Consultant
(7/1996 - 8/1997)
System Design/Debug:
Designed system boards and debugged the core logic
chipsets for 486, Pentium and P6 Motherboards.
System Level Test Hardware Design:
Designed an ISA Exerciser Hardware for validation and
testing of core logic chipsets.
Wipro Inc: Senior Engineer, R&D Hardware (7/1994 - 7/1996)
PC Motherboard Design and Debug:
Designed a 100 MHz Pentium motherboard based on the
Intel Triton Chipset. The features included onboard Ethernet and Display
Controllers.
Designed a Dual 100 MHz P54C motherboard based on Intel
Neptune Chipset.
Networking Hardware Design:
Designed a 155 Mbps ATM switch and a 100VG Anylan
Switch.
Education
Master
of Science, Electrical Engineering
(2004-2006)
Stanford
University, California
Bachelor
of Science, Electronics and Communication (1990-1994)
Regional
Engineering College, Tiruchirapalli, India
References
References
available upon request
Contact this candidate