Project Management

Ruisheng Wang

SMART Interconnects Group

Department of EE-Systems

****, ********* ***., *** ***

Los Angeles, CA 90089-2562

http://www-scf.usc.edu/~ruishenw

Cell: 213-***-****

Email: abp92a@r.postjobfree.com

Research Interests

Current Interests Onchip Network for Multi/Many-core Architecture, Onchip Resource (cache and memory

controller) Management in Chip Multiprocessor

Previous Interests High Performance Internet, High-Speed Router Design (Switch Architecture and Packet

Scheduler)

Education

Sep 2009-Current PhD student, Computer Engineering

University of Southern California, Los Angeles (GPA 3.835/4.0)

Sep 2006-Jul 2009 Master of Science, Computer Science & Technology

Tsinghua University, Beijing, China (GPA 88.78/100)

Sep 2002-Jul 2006 Bachelor of Science, Computer Science & Technology

North China University of Technology, Beijing, China (GPA 86/100)

Publications

1. Lizhong Chen, Ruisheng Wang, Timothy Mark Pinkston, Critical Bubble Scheme: An Efficient

Implementation of Globally-aware Network Flow Control, in Proceedings of the 25th IEEE International

Parallel & Distributed Processing Symposium (IPDPS 2011)

2. Yuho Jin, Ruisheng Wang, Woojin Choi, Timothy Mark Pinkston, Thread Criticality Support in On-Chip

Networks, in Proceeding of the 3rd International Workshop on Network On Chip Architectures (NoCArc

2010)

3. Ruisheng Wang, Youjian Zhao, Hongtao Guan and Guanghui Yang, HOBRP: A Hardware Optimized

Packet Scheduler that Provides T unable End-to-end Delay Bound, in Proceedings of 17th IEEE International

Workshop on Quality of Service (IWQoS 2009)

4. Ruisheng Wang and Youjian Zhao, Achieving 100% Throughput in a Two-stage Multicast Switch, in

Proceedings of the 23rd International Conference on information Networking (ICOIN2009)

5. Zhenhua Liu, Xiaoping Zhang, Youjian Zhao, Ruisheng Wang, A Performance Analysis Framework for

Routing Lookup in Scalable Routers, in Proceedings of the 23rd International Conference on information

Networking (ICOIN2009)

Projects

May2011

Coordinated Management for Cache Capacity and Memory Bandwidth in CMP --advisor

-Current

Prof. Timothy M. Pinkston

As new multi-threaded usage models such as virtualization and consolidation take advantage of multiple cores in

CMP architectures, the impact of shared resource contention between VMs and user-level applications introduces

Quality of Service(QoS) concerns and challenges. Our goal of this research is to manage multiple shared CMP

resources in a coordinated fashion to optimize system level performance objectives.

May 2010-May 2011

Thread Criticality in On-Chip Networks -advisor Dr. Yuho Jin

In multi-threaded application, the critical thread may delay all the other threads due to the synchronizations. We

proposed to dynamically build fast bypass path for critical threads, to boost overall system performance.

2011 Spring

Optimizing LU Decomposition in GPU (course project)

We implemented and analyzed the LU decomposition algorithm in Nvida GPU platform.

2010 fall

Access Patten Aware Cache Placement in a Hybrid Shared/Private NUCA (course project)

I proposed an intelligent replication policy based on a runtime cache block classification mechanism in a hybrid

shared/private NUCA. Cache blocks are classified into three groups: private, infrequently updated shared and

frequently updated shared. The first two groups are organized into private caches to improve performance while

the last one is organized into shared cache to reduce coherence overhead. The proposed mechanism was evaluated

with the trace of multi-threaded applications in PARSEC benchmark suite.

2010 Spring

Evaluation of DRAM power management algorithms in CMP environment (course project)

The efficiency of most DRAM power management algorithms is highly depended on its accuracy of memory

access prediction. Memory accesses in CMP are lack of locality, which make them hard to be predicted. The goal

of this project is to analyze the efficiency of three DRAM power management algorithms in the context of Chip

Multiprocessor. We re-evaluated three power management algorithms (LRU-Greedy, LRU-Smooth, LRU-

Ordered) in a 16 core CMP environment with a full system simulator SIMICS with GEMS.

2010 Spring

Comparison of Virtual and Physical Express Topologies in GARNET (course project)

We compared Express Virtual Channel (virtual bypasses) and Flatten Butterfly (physical bypasses) under various

synthetic and realistic (PARSEC benchmarks in SIMICS) traffic in GARNET.

Apr 2008-

FPGA-based switching system -Advisor: Prof. Youjian Zhao

Jul 2009

Master Graduation Project

I designed and implemented a 4 4 buffered crossbar in a FPGA chip. The crossbar has four GbE ports with

round-robin scheduler for both input and output. The design was synthesized by Quartus II and verified by

ModelSim.

Oct 2007-

CNGI backbone network monitoring and performance analyzing system

Nov 2008

(Part of China Next Generation Internet (CNGI) Project)

-Advisor: Prof. Youjian Zhao

The job of our hardware group in this project is to design a network device, which can distribute the network

traffic from an OC192 link to eight Gigabit Ethernet ports according to pre-defined rules (e.g. forward a particular

flow to a particular port). As a core member of this project, I wrote the drivers for the hardware (e.g., configuring

framers (PM5390/IXF1104) and custom FPGA, implementing CPU interrupts (MPC750)) and command-line

user interface for the system. I also implemented a packet forwarding function in a FPGA, and performed system

debugging in latter stage of the project.

Skills

Projects in C/C++ with MPI and OpenMP CUDA, Java (Jxta, JMP), VHDL,

Familiar with Python, Visual Basic, SHELL, TCL, ASP SQL, HTML,

Tools Simics/GEMS, Gem5, Tornado (VxWorks), Visual Studio, Eclipse, NS2(network

simulator), Matlab, Cadence, HSpice, QuartusII, ModelSim

Coursework (all taken from USC)

Computer Systems Architecture (EE557) Special Topics in Energy Efficiency and Reliability in ICT (EE599)

Parallel Programming (CS503) Broadband Network Architecture (EE555)

Interconnection Networks (CS659) Advanced Operating Systems (CS555)

VLSI System Design (EE477L/EE577a) Parallel and Distributed Computing (EE657)

Advanced Topics in Micro-architecture (EE653) Analysis of Algorithms (CS570)

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