Self-Compensating the Effect of Defect Generation in Advanced CMOS Substrates

Ahmad Ehteshamul Islam and Muhammad Ashraful Alam

School of Electrical and Computer Engineering, Purdue University

West Lafayette, IN 47906, USA

Phone: 765-***-**** Fax: 765-***-**** E-mail: abp7pk@r.postjobfree.com, abp7pk@r.postjobfree.com

The classical circuit-level BTI analysis [6-10, 15-17] and their

ABSTRACT

optimization study [7, 18-21] have one significant drawback: these

Time-dependent degradation of transistor parameters is one of the approaches begin with an experimentally calibrated SPICE model of

threshold voltage shift VT. Next one estimates the variation in

major reliability concerns in current CMOS technologies. Transistor

effective mobility ( eff) using various approximate expressions that

parameters, e.g. threshold voltage, drain current, etc. change due to

always predict a decrease in eff (i.e., negative eff) due to

the formation of defects at the oxide/Si interface; as well as due to

degradation [8, 22]. Taken together, degradation in eff as well as VT

charge trapping into defects present within the bulk of the dielectric

result in overall degradation in drain current (i.e. ID > 0

ID ~ 0

ID

ID(min)

V

7. CONCLUSION

MOS technology has so far evolved to maximize transistor s

VT VT

performance by introducing new concepts/ materials. Here, we

(a) (b)

V1 V1

speculate that the new substrate materials (e.g., strained-Si, III-V,

VG VG

VT0 VT0

VDD VDD

etc.) currently being studied for performance improvement, can also

VT -compensated M OS

Classical MOS

provide better resilience against the effects of defect formation.

Increase in negative steepness of eff - Eeff relationship or smaller

Fig. 8: Transfer characteristics of (a) classical and (b) VT- compensated

gm,ON (i.e., flatter ID-VG) has been identified as the requirement for

MOS transistors. Classical transistor handles VT using an extra guard-band

such self-compensation, which is easily achieved in strained/III-V

voltage (VDD-V1), which can be reduced using VT compensation with small

transistors. The use of such degradation free technology would not

gm,ON.

only simplify IC design, but also help reduce the supply voltage (and

power dissipation) by significantly curtailing the guard -band

necessary to account for VT in classical transistors.

6. OBTAINING SELF-COMPENSATION

ACKNOWLEDGEMENTS

We have now established that large or small gm,ON as a

We gratefully acknowledge NCN for computational resources,

requirement for designing self- compensated transistors. As we have

BNC for experimental facilities, and TSMC, AMAT, NCN, NRI for

discussed in [23], this can be achieved by increasing through

financial support during this work. In addition, Ahmad E. Islam

uniaxial strain. Uniaxial strain reduces inter-valley phonon scattering

acknowledges his discussions with Prof. Mark S. Lundstrom (Purdue

by introducing valley-splitting [30], and therefore makes surface

University) and Prof. Kevin Cao (Arizona State University) on

roughness scattering (having larger -E steepness [27] compared to

related issues.

the phonon component) the dominant component of the eff - Eeff

characteristics. As a result, of the overall eff - Eeff characteristics

REFERENCES

need to be increased for achieving self-compensation [23].

[1] K. Bernstein, D. J. Frank, A. E. Gattiker, et al., "High-

Moreover, since similar reduction in phonon scattering (hence an

increase in ) is expected at low temperature, self-compensation can performance CMOS variability in the 65-nm regime and

also be present in cryogenic electronics [31]. Encouragingly, the beyond," IBM Journal of Research and Development, vol. 50,

recent reports of ID-VG characteristics in Intel s 45-nm strained MOS pp. 433-449, Jul-Sep 2006.

technology [5] and III-V transistors [32] indicate the presence of

[2] A. E. Islam, H. Kufluoglu, D. Varghese, et al., "Recent Issues

large or small gm,ON. Thus, advanced substrates involving strained-

in Negative Bias Temperature Instability: Initial Degradation,

Si and III-V show the possibility of self-compensating VT with

Field-Dependence of Interface Trap Generation, Hole Trapping

reduced use of guard-band or any complicated circuit-level

Effects, and Relaxation," IEEE Trans. on Elec. Dev., vol. 54,

optimization.

pp. 2143-2154, 2007.

[3] G. Ribes, J. Mitard, M. Denais, et al., "Review on high-k power microprocessors under dynamic workloads," IEEE/ACM

dielectrics reliability issues," IEEE Trans. on Device and International Conference on CAD, pp. 721-725, 2002.

Materials Reliability., vol. 5, pp. 5-19, MAR 2005. [19] J. W. Tschanz, J. T. Kao, S. G. Narendra, et al., "Adaptive

[4] D. Heh, C. D. Young, and G. Bersuker, "Experimental body bias for reducing impacts of die-to-die and within-die

evidence of the fast and slow charge trapping/detrapping parameter variations on microprocessor frequency and

processes in high-k dielectrics subjected to PBTI stress," IEEE leakage," IEEE Journal of Solid-State Circuits, vol. 37, pp.

Electron Device Letters, vol. 29, pp. 180-182, Feb 2008. 1396-1402, Nov 2002.

[5] S. Pae, M. Agostinelli, M. Brazie, et al., "BTI reliability of 45 [20] K. Kang, K. Kim, and K. Roy, "Variation resilient low-power

nm high-k plus metal-gate process technology," International circuit design methodology using on-chip phase locked loop,"

Reliability Physics Symposium Proceedings, pp. 352-357, ACM/IEEE Design Automation Conference, pp. 934-939, 2007.

2008. [21] M. Agarwal, B. C. Paul, M. Zhang, et al., "Circuit failure

[6] K. Kang, H. Kufluoglu, K. Roy, et al., "Impact of Negative prediction and its application to transistor aging," Proceedings

Bias Temperature Instability in Nano-Scale SRAM Array: of IEEE VLSI Test Symposium, pp. 277-284, 2007.

Modeling and Analysis," IEEE Trans. on Comp.-Aided Design [22] B. C. Paul, K. Kang, H. Kufluoglu, et al., "Impact of NBTI on

of ICs and Systems, vol. 26, pp. 1770-1781, OCT 2007. the temporal performance degradation of digital circuits," IEEE

[7] B. C. Paul, K. H. Kang, H. Kufluoglu, et al., "Negative bias Elec. Dev. Lett., vol. 26, pp. 560-562, AUG 2005.

temperature instability: Estimation and design for improved [23] A. E. Islam and M. A. Alam, "On the possibility of

reliability of nanoscale circuits," IEEE Trans. on Comp.-Aided degradation-free field effect transistors," Appl. Phys. Lett., vol.

Design of ICs and Systems, vol. 26, pp. 743-751, APR 2007. 92 (173504), Apr 28 2008.

[8] W. P. Wang, V. Reddy, A. T. Krishnan, et al., "Compact [24] Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices:

Modeling and simulation of circuit reliability for 65-nm CMOS Cambridge University Press, 1998.

technology," IEEE Trans. on Device and Materials Reliability, [25] A. E. Islam, V. D. Maheta, H. Das, et al., "Mobility

vol. 7, pp. 509-517, Dec 2007. Degradation Due to Interface Traps in Plasma Oxinitride

[9] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "Impact of PMOS Devices," in Int. Reliability Phys. Symp., 2008, pp. 87-

NBTI on SRAM read stability and design for reliability," 96.

Proceedings of International Symposium on Quality Electronic [26] A. T. Krishnan, V. Reddy, S. Chakravarthi, et al., "NBTI

Design, pp. 210-215, 2006. impact on Transistor and Circuit: Models, Mechanisms and

[10] K. Kang, K. Kim, A. E. Islam, et al., "Characterization and Scaling Effects," in Int. Elec. Dev. Meeting (IEDM), 2003, pp.

estimation of circuit reliability degradation under NBTI using 349-352.

on-line I-DDQ measurement," IEEE Design Automation [27] S. Takagi, A. Toriumi, M. Iwase, et al., "On the Universality of

Conference, pp. 358-363, 2007. Inversion Layer Mobility in Si MOSFETs .1. Effects of

[11] J. J. Kim, R. Rao, S. Mukhopadhyay, et al., "Ring oscillator Substrate Impurity Concentration," IEEE Trans. on Elec. Dev.,

circuit structures for measurement of isolated NBTI/PBTI vol. 41, pp. 2357-2362, DEC 1994.

effects," Proceedings of IEEE International Conference on [28] S. Villa, A. L. Lacaita, L. M. Perron, et al., "Physically-based

Integrated Circuit Design and Technology, pp. 163-166, 2008. model of the effective mobility in heavily-doped n-

[12] V. Reddy, A. T. Krishnan, A. Marshall, et al., "Impact of MOSFET's," IEEE Trans. on Elec. Dev., vol. 45, pp. 110-115,

negative bias temperature instability on digital circuit JAN 1998.

reliability," in Int. Reliability Phys. Symp., 2002, pp. 248-254. [29] M. S. Lundstrom, "On the mobility versus drain current

[13] Y. H. Lee, W. McMahon, N. Mielke, et al., "Managing bias- relation for a nanoscale MOSFET," IEEE Elec. Dev. Lett., vol.

temperature instability for product reliability," Proceedings of 22, pp. 293-295, JUN 2001.

International Symposium on VLSI Technology, pp. 52-53, [30] S. E. Thompson, G. Y. Sun, Y. S. Choi, et al., "Uniaxial-

2007. process-induced strained-Si: Extending the CMOS roadmap,"

[14] M. Alam, "Reliability- and process-variation aware design of IEEE Trans. on Elec. Dev., vol. 53, pp. 1010-1020, May 2006.

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