Design Technology

Self-Compensating the Effect of Defect Generation in Advanced CMOS Substrates

Ahmad Ehteshamul Islam and Muhammad Ashraful Alam

School of Electrical and Computer Engineering, Purdue University

West Lafayette, IN 47906, USA

Phone: 765-***-**** Fax: 765-***-**** E-mail: *******@****.***, ****@******.***

The classical circuit-level BTI analysis [6-10, 15-17] and their

ABSTRACT

optimization study [7, 18-21] have one significant drawback: these

Time-dependent degradation of transistor parameters is one of the approaches begin with an experimentally calibrated SPICE model of

threshold voltage shift VT. Next one estimates the variation in

major reliability concerns in current CMOS technologies. Transistor

effective mobility ( eff) using various approximate expressions that

parameters, e.g. threshold voltage, drain current, etc. change due to

always predict a decrease in eff (i.e., negative eff) due to

the formation of defects at the oxide/Si interface; as well as due to

degradation [8, 22]. Taken together, degradation in eff as well as VT

charge trapping into defects present within the bulk of the dielectric

result in overall degradation in drain current (i.e. ID > 0

ID ~ 0

ID

ID(min)

V

7. CONCLUSION

MOS technology has so far evolved to maximize transistor s

VT VT

performance by introducing new concepts/ materials. Here, we

(a) (b)

V1 V1

speculate that the new substrate materials (e.g., strained-Si, III-V,

VG VG

VT0 VT0

VDD VDD

etc.) currently being studied for performance improvement, can also

VT -compensated M OS

Classical MOS

provide better resilience against the effects of defect formation.

Increase in negative steepness of eff - Eeff relationship or smaller

Fig. 8: Transfer characteristics of (a) classical and (b) VT- compensated

gm,ON (i.e., flatter ID-VG) has been identified as the requirement for

MOS transistors. Classical transistor handles VT using an extra guard-band

such self-compensation, which is easily achieved in strained/III-V

voltage (VDD-V1), which can be reduced using VT compensation with small

transistors. The use of such degradation free technology would not

gm,ON.

only simplify IC design, but also help reduce the supply voltage (and

power dissipation) by significantly curtailing the guard -band

necessary to account for VT in classical transistors.

6. OBTAINING SELF-COMPENSATION

ACKNOWLEDGEMENTS

We have now established that large or small gm,ON as a

We gratefully acknowledge NCN for computational resources,

requirement for designing self- compensated transistors. As we have

BNC for experimental facilities, and TSMC, AMAT, NCN, NRI for

discussed in [23], this can be achieved by increasing through

financial support during this work. In addition, Ahmad E. Islam

uniaxial strain. Uniaxial strain reduces inter-valley phonon scattering

acknowledges his discussions with Prof. Mark S. Lundstrom (Purdue

by introducing valley-splitting [30], and therefore makes surface

University) and Prof. Kevin Cao (Arizona State University) on

roughness scattering (having larger -E steepness [27] compared to

related issues.

the phonon component) the dominant component of the eff - Eeff

characteristics. As a result, of the overall eff - Eeff characteristics

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