Engineer Design

Location:

Oakland, CA

Posted:

December 10, 2012

Contact this candidate

Resume:

Resume for Dipl.-Ing. Andreas Schmidt

Personal Dipl.-Ing. Andreas Schmidt (MSEE)

Oakland, CA, USA

Mobile phone: +1-408-***-****

em@il: ***@****.**

homesite: http://www.asic.cc

Objective Application / Technical Marketing / Systems / ASIC / FPGA / IP

Engineer / Manager / Consultant

in an innovative, industry-leading company

Summary Experience with VHDL/Verilog - synthesis /simulation /ASIC design tools since 1994

Gate level simulation experience since 1992

Experience with XILINX FPGA technology and tools since 1989

Circuit and system design experience since 1984

Experience with high speed serial connections (SerDes links) for inter-chip communication since 1991

Used distributed parallel processing technology since 1991

Double Data Rate (DDR) design experience since 1992

Computer / system / network administrator experience since 1983 (UNIX, Windows)

Pro-audio engineering, sound reinforcement, and music technology experience since 1986

Special Written highly portable, parameterized, modular, and scalable code in Verilog and VHDL

for efficient portability, reusability, technology migration, and maintenance

skills & ASIC to FPGA, FPGA to ASIC, and IP migration experience

highlights Strong team building, facilitation, and mentoring skills

Worked effective with cross functional international teams and brigded gaps when needed

German engineering education and precision together with strong work ethics

Diligent project management, analytical problem solving, and facilitative leadership skills

Dual citizenship, multi-lingual

International working, presentation, and conference experience

Experience 2004 - present: ASIC.CC, Oakland, CA, USA

Founder / Principal consultant

Real-time audio/video over ethernet system design and consulting

Serial high speed connections (SerDes links) and protocols for inter-chip and systems connectivity

Quality and efficiency management including CVS support

Design, implementation, simulation and debugging services for Xilinx FPGA designs

VHDL to Verilog and Verilog to VHDL code conversion

ASIC to FPGA, FPGA to ASIC, and IP migration support

semiconductor technology selection and consulting

Team building and facilitation for cross functional design teams

CAD/EDA tool support, license administration, configuration, and consulting

Concept, design, and implementation of IP and generic design libraries (VHDL/Verilog2001) for cross

platform designs

Third-party code (VHDL/Verilog2001) design review, analysis, debug, and correction

Design reviews, consistency checks, and project management

Lab debug support (TDR, transmission lines, signal integrity, Chipscope)

Technical trainings, technical marketing, and technology representation at conferences and tradeshows

Experience 2005 2010: XILINX, San Jose, CA, USA

Staff Serdes Applications Engineer

Authored, edited, managed Virtex-5 GTP transceiver user guide [UG196] creation

(SerDes on Virtex-5 LXT & SXT devices)

Authored, edited, managed Virtex-5 GTX transceiver user guide [UG198]

(SerDes on Virtex-5 FXT & TXT devices)

Authored, edited, managed Virtex-6 GTX transceiver user guide [UG366]

(SerDes on Virtex-6 LXT & SXT devices)

Authored, edited, managed Spartan-6 GTP transceiver user guide [UG386]

(SerDes on Spartan-6 LXT devices)

Authored, edited, managed 7 Series FPGAs Transceivers User Guide [UG476]

(SerDes on 7 Series FPGAs)

Provided worldwide SerDes trainings to SystemIO specialists and Field Application Engineers (FAE)

Supported key customers worldwide via escalation, implementation assistance, and on-site support

board, signal & power integrity analysis, and system design reviews, root cause analysis

Reviewed designs of SerDes building blocks and provided feedback to IC-design

2004 2005: CloudShield Technologies, Sunnyvale, CA, USA

Senior Design Engineer

Specified, designed, implementated, simulated, debugged, managed multiple FPGA (Xilinx Virtex II Pro/

ProX) designs for their flagship Network Packet Processing / Network security product CS2000

Shipped successfully the designs as part of the first General Public Availability Release (Gigabit Ethernet,

PCI (32bit/66MHz), bus interface to Intel IXP 2800 NPU, I2C, SONET OC48 framer, SPI 4.2 & SPI3

interfaces, inter-chip communication (2.5 Gigabit) using Xilinx Rocket-IO transceiver on board level and

on system level via backplane, SONET OC48 Overhead processing (at line rate with low latency), dynamic

re-configuration of FPGAs via software)

Written testbenches / implementation code using Verilog2001 and simulation/implementation scripts

Facilitated and supported CVS (version control system) use inside the hardware group

Written automatic lab test environment for board bring-up using PERL (RedHat Enterprise Linux 3.0)

Debugged and corrected successfully third party code (Verilog) with insufficient and contradicting

documentation available

Board bring-up and lab debugging in close interaction with firmware and board designers

CAD/EDA tool support, license administration / configuration, and consulting

Used ModelSim SE, Synplify Pro, Mentor Precision Synthesis, Xilinx ISE tool flow, Synopsys VirSim/

VCS, HyperLynx, and HSPICE tools

2001 2004: GIBSON Labs Technology Group, Sunnyvale, CA, USA

(a Research and Development Division of GIBSON Guitar, Nashville, TN, USA)

Senior ASIC Engineer

Architected, designed, simulated, implemented, managed the digital part of a mixed signal ASIC, which

implemented the GIBSON MaGIC protocol in hardware (packet processing of real-time audio/video data

on the MAC layer and above (100 MBit full duplex), interfacing to 24bit codecs) for professional audio/

video applications (studio/concert/broadcast mixing hardware)

Developed generic design library and IP of the MaGIC transfer protocol

Consulted, trained team members in-house on ASIC/semiconductor technology

CAD/EDA tool support, license administration, system administration and support

Written daily report to the CEO of GIBSON GUITAR Henry Juszkiewicz

Optimized an array of six magnetic micro transducers (Output voltage, SNR, frequency response, channel

separation) using Finite Element Method Magnetics (FEMM) and SPICE (hexagonal magnetic pickup for

the GIBSON MaGIC digital guitar)

Represented, evangelized, demonstrated MaGIC technology at the AES, CES, Frankfurter Musikmesse,

Intel Developer Forum, NAMM show, and for music industry celebreties

Experience 2000 2001: Blue Iguana Networks (Nuvation spin-off), Fremont, CA, USA /

Nuvation Labs Corporation, San Jose, CA, USA

Senior Hardware Engineer

Concepted, specified, architected, implemented, managed the BI Logic engine core in VHDL (packet pro-

cessing at the MAC layer and above at 100Mbit full-duplex)

Architected, developed, managed BI system technology on the target side (remote administration/reconfig-

uration of FPGAs and systems via a validated, encrypted WAN connection with local fallback)

Definition, Technical Marketing of future BI technology (patent contribution/co-authoring, roadmap)

Technical Lead

Designed, simulated, managed, integrated a Voice-over-IP design in Verilog (bidirectional 100Mbit Ether-

net to T1/E1 bridge) for an optical network device (ONS for Alloptic)

Designed, simulated, managed, released a real-time video data processing and compression design for a jet

flight display in VHDL (interface via TAXI SerDes)

Mentoring, team leading, in-house training, and consulting

CAD/EDA tool support, license administration, system administration, and support

1994 2000: Andreas Schmidt ASIC-Design, Technical Consulting, Hard- & Software,

Bochum, Germany

Entrepreneur / Consultant

Project work concerning digital circuit/system-design (using Xilinx Foundation, ALDEC Active-HDL,

Synopsys, Synplicity, Mentor tools, Protel PCB, etc.), (VHDL, Verilog, mixed)

Architected, developed, sold computer solutions for specialized environments (medical technology)

Dealership authorizations: SUN-VAR, Apple-, Microsoft-, Microsoft education-dealer

Provided quality and efficiency management for the whole design process

Performed system administration of heterogeneous networks (SUN / Apple / WinNT - platforms)

Conducted technical consulting concerning networking, computer solutions, system design

1992 1996: Institute Electron Devices and Integrated Circuits,

Ruhr-Universit t Bochum, Germany

Assistant to System administrator (1 year)

Administrated workstations running SunOS 4.1.3, Solaris 2.4, ULTRIX, Linux, MicroVMS

Programmed under SunOS, Solaris, ULTRIX

Installed, configured, administrated IC design development systems (Cadence, Synopsys, XILINX, etc.)

Teaching Assistant: VLSI IC-design II design course (practical lab digital circuits) (3 years)

Developed course material, reviewed student designs,

Trained MSEE students on VLSI ICdesign techniques, tools, and methodologies using:

Xilinx FPGAs, Xilinx XACT, Synopsys tools, SunOS 4.1.3, SUN SPARC 10/20

Mietec CMOS standardcells(1.2 ), Cadence Edge IC-design tools, ULTRIX, DECstation5000

MMI CMOS gate arrays, Silvar-Lisco SL2000, MicroVMS, MicroVAXII

1991 1994: NEUROTECH GmbH, Oberhausen, Germany

Developer of Digital circuits/systems

Designed interfaces to Hell/Linotype/Heidelberg repro graphic scanner/recorder

Used INMOS Transputer and XILINX FPGA technology (XC3090, XC4010, XACT), DATA-I/O Dash

FutureNet, ViewLogic Workview

Designed system for real-time pre-press data processing using SerDes links, distributed parallel processors

Managed the project of the schematic-converter Dash2View (DataIO Dash -> ViewlogicWorkview)

Developed test programs using Pascal and Occam

Education Ruhr-Universit t Bochum, Germany: Dipl.-Ing. Elektrotechnik 1999/2000 (MSEE degree)

Master-Thesis:

Realization of an efficient acquisition of measurement-data and control of a halfbridge-current-inverter for

the operation of a Superconducting Magnetic Energy Storage system

Education continuation:

Project Management (PM) classes at the San Jose State University as part-time student in order to reinforce

my project management skills and to optimize them for the US (100% personally funded)

Employer funded classes and courses:

PLL analysis & design (US Santa Cruz extension)

High speed Noise & Grounding (Dr. Howard Johnson)

Managing At XILINX (MAX)

Managing Time and Multiple Priorities (Effective Training Associates)

Managing within the Law I&II

Breaktrough Project Management (Effective Training Associates)

Presenting for Action (Boyers Communication Group)

Writing for Action (Boyers Communiction Group)

Facilitative Leadership (Interaction Associates)

various presenter workshops, briefings, trainings

References Inside my profile on LinkedIn: http://www.linkedin.com/in/asics

Skill set FPGA, ASIC, XILINX, VHDL, Verilog, Pascal, Modula2, Ada, C, SUN, Solaris, Apple, Windows NT, sys-

tem administration, PCB layout, signal integrity, Microsoft, TCP/IP, framer, system design, verification, syn-

by thesis, simulation, RTL, Synopsys, Cadence, Mentor, Aldec, ModelSim, Synplicity, Exemplar, Active-HDL,

keywords CAD, EDA, FlexLM, licensing, SunOS, ULTRIX, Linux, VMS, CMOS, standard cells, gate arrays, Silvar-

Lisco, XACT, PDF, Acrobat, Adobe, FrameMaker, Protel, ORCAD, HTML, PHP, csh, cshell, bourneshell,

kornshell, SOC, digital design, LAN, WAN, gateway, switch, router, VoIP, packet processing, DDR, SRAM

interface, DDR RAM interface, Transputer, INMOS, Viewlogic, WorkView, Dash FutureNet, Superconduc-

tor, german, mentoring, patent, consulting, Dipl.-Ing., MSEE, system administration, network administrator,

wirespeed, project management, Blue Iguana, HDMI, SerDes, teaching, international, presentations, trade-

show representations, adaptive computing, DSP, digital filter, multi-lingual, ATM, SONET, SDH, DLL,

clock recovery, logic design, ASIC design, heterogeneous networks, gate level, circuit design, Hell, Linotype,

Heidelberg, repro graphic, scanner, recorder, graphic processing, picture processing, medical technology,

optical network, Globetrotter, video processing, speech processing, sound processing, VLSI, HDL, Vera, tim-

ing analysis, design flow, tool configuration, design flow administration, testbenches, TCL/TK, object-ori-

ented design, OOHD, multi-million gates, double data rate, chipscope, methodology, hierarchical, modular,

symmetrical, locality, place, route, P&R, physical layout, floor planning, memory compiler, timing-driven,

logic-synthesis, physical verification, DRC, LVS, schematic, logic simulation, EDIF, SDF, SMES, ATMEL,

prototype, DFT, BIST, BILBO, LFSR, scan path, dual citizenship, signature analysis, synchronous design,

scripting, scripts, shell scripts, MAC, OSI model, IEEE, audio, VAR, behavioral, model, emulation, MMI,

Mietec, GIBSON, GUITAR, MaGIC, mixed signal, codec, real-time audio

Dual US: United States citizen

EU: German citizen (working permit for the whole European Union)

citizenship

Version 2011.09.13.16.59 (the latest version of this resume can always be found at: http://www.asic.cc

at conferences and tradeshows

Contact this candidate