Design Project Manager

RAVI JENKAL ********@****.***

http://www*.ncsu.edu/~rsjenkal/

****/*** ***** ***** ****, Raleigh NC 27606

OBJECTIVE:

Full-time Digital (Architecture, Flows, Design and Validation) position for Energy Efficient Systems-on-a-Chip, Low Power

and/or High Speed DSP Algorithm Implementation, Processor Architecture Implementation, High-level Performance

Estimation, ASIC Design Methods and 3D Integrated Circuit Design (3DIC) Methods and architectures.

EDUCATION:

North Carolina State University, Raleigh, NC.

PhD Candidate in Computer Engineering. (Aug 2004 present). [GPA: 3.85/4.0]

Advisor: Dr Rhett Davis, Director, Methodologies for User-friendly SoC Experimentation (MUSE), ECE Dept NCSU.

Research Summary: Architecture and design methodology of energy-efficient next generation MIMO SoCs. We focus on the

determination of solutions in the algorithm-architecture design space for improved bits/sec/mW performance of MIMO

decoders. This is of particular importance as we move down to lower technology nodes and graduate towards mobile

applications and high throughput standards such as 3G/4G. This work also focuses on the determination of a methodology for

systematic exploration of the design space to converge to the best solution (algorithm&/architecture) for a given set of speed,

power and performance constraints.

North Carolina State University, Raleigh, NC.

Master of Science in Computer Engineering. (Aug 2002 - Aug 2004). [GPA: 3.91/4.0]

Advisor: Dr Rhett Davis, Director, Methodologies for User-friendly SoC Experimentation (MUSE), ECE Dept NCSU.

Sri Jayachamarajendra College of Engineering, India.

Bachelor of Engineering (with Distinction) in Electronics and Communication Engineering. [GPA: 4.0/4.0]

PUBLICATIONS:

Chris Mineo, Ravi Jenkal, Samson Melamed, W. Rhett Davis, "Inter-Die Signaling in Three Dimensional Integrated

Circuits", To appear in IEEE Custom Integrated Circuits Conference (CICC), September 21 - 24, San Jose, California.

Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander,"Automated Design Space Exploration for DSP

Applications", Accepted to The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology.

Meeta Yadav, Ravi Jenkal, Paul Franzon, Bob Oden, Pete Lafuci, "Developing Infrastructure for an Advanced

Application Specific Integrated Circuit Verification Course", to appear in 7th European Workshop on Microelectronics

Education (EWME), May 28-30, 2008, Budapest, Hungary.

Ravi Jenkal, W. Rhett Davis, "An Architecture for Energy Efficient Sphere Decoding", In International Symposium on

Low Power Electronics and Design (ISLPED 2007), Portland, OR, August-27-29, 2007.

J. E. Stine, I. Castellanos, W. R. Davis, P. D. Franzon, M. Bucher, S. Basavarajaiah, J. Oh, R. Jenkal, "FreePDK: An

Open-Source Variation-Aware Design Kit", In International Conference on Microelectronic Systems Education (MSE

2007), San Diego, CA, June 2 - 4, 2007.

Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander, "Automated Architectural Exploration for Signal

Processing Algorithms" In IEEE Workshop on Signal Processing Systems (SiPS 2006), Banff, AB, Canada, October 2- 4,

2006.

Ravi Jenkal, Hao Hua, Ambarish Sule, Rhett Davis, "Architecture for Energy Efficient Sphere Decoding", In IEEE 17th

ASIC/SOC Conference (SOCC 2006), Austin, TX, USA, Sept. 24-27, 2006.

Hao Hua, Chris Mineo, Kory Schoenfliess, Ambarish Sule, Samson Melamed, Ravi Jenkal, Rhett Davis, "Exploring

Compromises among Timing, Power and Temperature in Three-Dimensional Integrated Circuits", In IEEE/ACM 43rd

Design Automation Conference (DAC 2006), San Fransisco, CA, July 24-28, 2006.

Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander, "Tool Integration for Signal Processing Architectural

Exploration" Presentation in IEEE Electronic Design Process Symposium (EDPS 2006), Monterey, CA, April 13-14, 2006

TAPEOUT EXPERIENCE:

Low Power Sphere Decoder in IBM 90nm process. Design Coded in Verilog RTL with scan-chains. Synthesis and pre-

layout performance measurements in Synopsys Design Compiler environment. Encounter based crosstalk aware design

flow used for RTL-GDSII implementation with the use of Celtic-NDC based crosstalk checks. Post-layout SPEF based

physical design measurements and timing checks. Design was finally imported into Cadence DFII framework for Calibre

based physical design verification. Interactive algorithmic, architectural and design flow in Perl with C++ and Tcl.

3DIC Low Power Sphere Decoder in 180nm MIT 3D SOI process. Synopsys Cadence design flow in the OpenAccess

framework developed at North Carolina State University used for RTL to GDSII flow.

RESEARCH PROJECTS:

Low Power Sphere Decoder design and implementation to test feasibility for 4G implementations. Implementation done

in both TSMC 0.18u and IBM 90nm technology nodes.

RAVI JENKAL ********@****.***

http://www4.ncsu.edu/~rsjenkal/

2500/202 Avent Ferry Road, Raleigh NC 27606

High Performance A-Posteriori Probability (APP) based Maximum Likelihood Detector (MLD) for HSDPA 3GPP-

compliant MIMO communication in TSMC 0.18u technology node. Coding in Verilog with Perl and C based algorithmic

performance testing and design space exploration.

Implementation of MLD APP with self testing structure on Xilinx XC2VP7 FPGA for design prototyping and use of

RS-232 based acquisition of data for software algorithmic performance measurements.

WORK EXPERINCE:

QUALCOMM Inc, Cary, NC.

Interim Engineering Intern, Hardware Design Group (May 2006 Aug. 2006)

Verification of Multi-processor System-on-a-Chip for next generation cellular service.

Used OpenVera based Verification Methodology, mixed-HDL simulations and Software Emulation in an automated

perl environment.

SPRINT, Kansas City, KS.

Intern, Installation and Major Projects Group, Western Operations (May 2003 Aug. 2003)

Project Manager for DSL installations in Minnesota and two Inter-exchange projects in Texas.

Responsibilities involved the timely completion of the projects assigned by job assignment and familiarization with all

stages and technical aspects of installation and working of DSL technology.

ECE DEPARTMENT, NORTH CAROLINA STATE UNIVERSITY, Raleigh, NC

Graduate Research Assistant ( Dec. 2006 present) PI: Prof. Paul Franzon

Creation of the ASIC Verification base for the EDA efforts at NCSU with Mentor Graphics based tooling support.

Design flow for low power/high performance SI-aware CAD flow for 180 nm 45nm ASIC designs. Automated

prototyping / evaluation flow based on Perl based tool stitching for Power, Area and Delay analysis. CACTI based

Memory generator (LEF, lib) for realistic evaluation of architectural choices.

Graduate Teaching Assistant

ECE 745: ASIC Verification (Aug. - Dec. 06) Instructor(s): Prof. Paul Franzon.

Instruction, grading and supervision of students in fundamentals of the ASIC verification process and constructs.

Particular focus in the use of SystemVerilog based verification with OOP, Coverage, Constraint Random Testing and

design of layered testbenches for maximum reuse.

ECE 520/464: Digital ASIC Design (Jan. - May. 04) Instructor(s): Prof. Paul Franzon.

Supervision of labs and instruction of students in fundamentals of Digital ASIC Design (HDL-Netlist). Particular

focus on the use of Verilog HDL for design and Synopsys Design Compiler synthesis.

ECE 746: VLSI System Design (Aug. - Dec. 05) Instructor(s): Dr. Rhett Davis.

Grading and instruction of students in fundamentals of design of digital VLSI systems with focus on device physics,

fabrication, design and layout methodology, integrated system architectures, timing and testing.

ECE 747: DSP Architecture (Jan. May. 06) Instructor(s): Prof. Winser Alexander.

Grading and instruction of students in design and analysis of DSP algorithms and implementations with focus on

exploration and evaluation of architectures for filter structures using SystemC and MATLAB.

ECE 792x: IC Design for Wireless Communication (Jan. - May. 05) Instructor(s): Dr. Kevin Gard.

Grading and instruction of students in analog IC system design considerations for wireless systems under Noise

Figure, Linearity and Gain constraints.

ECE 406: Design of Complex Digital Systems (Aug. - Dec. 04, Jan. - May 06) Instructor(s): Dr. Rhett Davis. ( 05);

Dr. Tom Bradicich ('05); Dr. Xun Liu ('04).

Supervision of labs and instruction of students in fundamentals of Digital Design and on the use of Verilog HDL for

design and synthesis.

ECE 212: Fundamentals of Logic Design (May - Jul. 04, May -Jul. 05) Instructor(s): Dr. David Bradley.

Grading and lab assistance for students in basics of logic design and use of chip sets for board level implementations.

RAVI JENKAL ********@****.***

http://www4.ncsu.edu/~rsjenkal/

2500/202 Avent Ferry Road, Raleigh NC 27606

SKILL SETS:

CAD tools: Cadence Analog Artist, Virtuoso, Hspice, Spectre RF, Synopsys Design Compiler, Primetime, PrimePower,

Mentor Graphics Questa/Modelsim, Xilinx ISE (Virtex II FPGA design flow), Simulink, Encounter crosstalk

aware design flow (RTL-GDSII), Calibre LVS/DRC/xRC, SignalStorm, VoltageStorm, Agilent ADS.

HDL/HVL: Verilog, VHDL, SystemVerilog, OpenVera, Specman Elite (E-language), SystemC.

Scripting: C, C++, Perl, Tcl, Python

Other: 8085/86/68HC11 Assembly Language, MATLAB.

PROFESSIONAL ACTIVITIES AND SERVICE:

Reviewer, SystemVerilog for Verification: A Guide to Learning the Testbench Language Features by Chris Spear.

Reviewer, IEEE Design and Test of Computers (DToC)

Student Member, IEEE

ACADEMIC PROJECTS:

Multiple Input Multiple Output (MIMO) algorithm implementation on Chip Multi-Processor (CMP) architecture. Group

project (3) using C++ on Simplescalar simulator.

Thermally aware 3DIC placement tool using sequential pairs. Group project (4) using C++ and Hspice.

Implementation of flat Fiduccia-Mattheyses algorithm for hyper-graph bi-section partitioning with focus on speed of

implementation for benchmark input graphs. Individual project in C++.

Implementation of simulated annealing placement using sequence pair technique with focus on speed of implementation

and quality (area) of final placement result. Individual project in C++.

Full custom design and layout of a 4-bit microprocessor with optimized area and speed. Team project involved complete

logic design and testing using Cadence Analog Artist, circuit simulation using HSPICE, layout using Cadence Virtuoso

for TSMC 0.25u technology.

Verilog implementation of Rasterizer in a simplified Black and White 3-D Graphics pipeline using Flat Shading. Group

project (2) focusing on area throughput optimization.

ASIC Verification of an out-of-order pipelined ALU. Creation of randomized self-checking environments in e using

Specman and Modelsim. Group project (2).

Cache Simulator in C for design & simulation of caches with victim cache suited for SPECint95 benchmarks. Individual

project using C.

Design and comparative analysis of bimodal, gshare and hybrid branch predictor structures suited to SPECint95

benchmarks. Individual project in C.

Construction and analysis of a simulator for an out-of-order superscalar processor based on Tomasulo s algorithm.

Individual project in C.

Design of 5 GHz LNA and down-converter mixer and associated DC bias circuits per specifications provided. Individual

project done on Cadence CDK design in Analog Artist and analysis using Spectre RF.

Transistor-level high-speed AC coupled transceiver design. Implementation involved the use of HSPICE and Cadence

suite to design minimal power-delay product structure of Kuhn s transceiver design for TSMC 0.18u technology.

Minimal power delay-product design of transistor-level high speed flip-flop (semi- dynamic) design. Implementation

involved the use of HSPICE and Cadence suite to design minimal power-delay product structure using TSMC 0.18u

technology.

Fully Pipelined LC3 Microcontroller design and synthesis.

RELEVANT COURSES:

Automated VLSI Design, VLSI System Design, ASIC Design, ASIC Verification, Digital Electronics, Computer Design and

Technology, Advanced Mircoarchitecture, Analog Electronics, IC Design for Wireless Communications, Digital Signal

Processing, Design of Interconnects and Packaging.

HONORS / ACTIVITIES:

Awarded Mentor Graphics Fellowship, Dec 2006 present.

Awarded Outstanding Teaching Assistant, ECE Department North Carolina State University, for 2005-2006.

Inducted to Eta Kappa Nu (HKN), National ECE Honor Society.

Awarded recognition by Visveswaraiah Tech University for academic excellence in the Electronics and Communication.

Awarded Certificate of Merit by the Central Board for Secondary Education, India for being in the top 0.1% of the test

takers (400,000 in total) in the National Physics examination.

RAVI JENKAL ********@****.***

http://www4.ncsu.edu/~rsjenkal/

2500/202 Avent Ferry Road, Raleigh NC 27606

REFERENCES:

Dr William Rhett Davis Kim O Donnell

Associate Professor, Director, Hardware Design Group (RTP),

Director, Methodologies for User-Friendly SoC Experimentation, Qualcomm

Department of Electrical and Computer Engineering ****@********.***

North Carolina State University

***********@****.***

Dr Paul Franzon

Distinguished Alumni Professor,

Director, Electronics Research Lab,

Department of Electrical and Computer Engineering

North Carolina State University

*****@****.***

VISA STATUS: F-1

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