Design Engineer

Gary Bazuin

****@***************.***

Summary

Thirty plus years experience in and knowledge of designing, building, and debugging electronics. Continuously ensure that

my knowledge of current technology and design tools is up-to-date. Assess technology and tools against my electrical design

knowledge, which includes having done schematics and VLSI layout by hand, to make sure the tools perform optimally to

produce the best designs. Through practical application of my theoretical, historical, and design tools knowledge, work with

systems engineers to generate the architecture to create detailed designs for products.

Professional Experience

Artech Information Systems, L.L.C. September 2010-present

Temporary contract position designing RTL for next generation multi-antenna wide band digital transmit and receive IC

solution. Designs include digital up/down converter with programmable fir filter, CIC filter and complex mixer.

Graychip/Texas Instruments, Member Group Technical Staff, 1992-2008 Note: TI bought Graychip, August 31, 2001.

When hired at Graychip, it was a three person fabless semiconductor company that used open source and in-house design

tools. Have expert knowledge of and experience on those tools and performed all software and hardware maintenance on my

Sun and Linux workstations. I formatted design rules for the layout tool, did library layout and characterizations, designed

and ordered parts for test fixture cards, and did anything else required to get chips out to fabrication. The GC2011, which is

still in the TI catalog, was created when Graychip was a three person company.

From 1992 through 2005 created the following digital signal processing (DSP) chips using Graychip custom tools to draw

schematics, simulate, and verify schematics to c-code models; and used an open source VLSI layout tool ( Magic) and Spice

simulator (T-Spice) to design VLSI circuits.

GC2011 GC3011 GC3021 GC4016 GC4116 GC5016

Supervised one person who helped complete top-level hand layout. Performed transistor level design and layout for gates;

RAMs and ROMs; and top-level layout when needed. Utilized Spice simulations of the gates, RAMs, and ROMs to create

library timing characterization. The chips implemented FIR filters; CIC filters; digital mixers; resamplers; control ports for

microprocessor control and programming; and interface circuits to get data into and out of the chips.

From mid 2005 through the end of 2007, worked on the GC5322 with a large team using TI ASIC design flow with Verilog

for RTL design; Synopsys tools for arithmetic IP ( DesignWare) and Verilog synthesis (Design Compiler); and Magma

(Mantle and Talus) tools for physical design. Used Magma and Synopsys (PrimeTime) tools for timing verification (STA).

The GC5322 is a cell phone base station digital up converter with crest factor reduction, Farrow resampler, and digital

predistortion.

From the end of 2007 to Sept 2008 I worked on the follow-on to the GC5322. Designed Verilog RTL of the DUC/DDC,

Farrow resampler, CIC and digital frequency hopping NCO and mixer. Did the preliminary physical design and timing

verification of the subchip.

ESL, Inc., Sunnyvale, CA 1984-1992

Hardware Program Manager: Various digital designs using Xilinx FPGA s; TMS302C30 DSP; and standard TTL, CMOS,

and ECL logic. VLSI design using Cadence tools to design custom chips for programmable decode of TDM bit streams.

ARGOSystems, Sunnyvale CA 1980-1983

Hardware design using 8085 microprocessors to control and interface to RF components for receiver systems.

Honeywell Inc, Minneapolis MN 1979-1980

Design Engineer in automatic test equipment group. Designed test equipment for inertial reference system of Boeing

757/767 using off the shelf and custom circuit cards for Motorola 6809 based EXOR-bus (predecessor to VMEbus) chassis.

Patents: 6078193, 6163172; www.patentstorm.us/inventors/Gary_John_Bazuin-1866554.html

Education: BSEE 1977; MSEE 1979; Michigan Technological University

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