Manager Engineer

JAMES T. DOYLE, PE

**** * **** ****** *****

Phoenix Arizona 85044

Email: *****.*.*****@*****.*** **********@***.***

Website: www.namyz.com

Work Phone: 480-***-****

Mobile Phone: 602-***-****

EDUCATION

Nova Southeastern University, Herzog School of Business Ft Lauderdale Florida,

DBA (on

going)

University of Illinois Champagne/Urbana University (Incomplete moved to Ft Lauderdale)

MSEE (18

hours) 1976

Nova Southeastern University, Herzog School of Business Ft Lauderdale Florida, MBA.

MBA 1991

University of Nebraska, School of Engineering Lincoln Nebraska

BSEE 1972

University of Miami, MacAurthor School of Engineering Coral Gables Florida

Pre Engineering (Freshman Year)

Christopher Columbus Boys Catholic Prep High School, Miami Florida Solitarian (4.0 GPA)

Nov. 2004 Virtuoso AMS Designer Training, Colorado, USA

Analog Design Course UCLA

Dec. 1996

University of Colorado Power Electronic Correspondence Course

Feb. 2006

Advanced Course on Simulink Model building by Mathworks

TI TMS2812 Training

Neo Circuit and DFM Training Cadence (Numerous Intel/Cadence Training courses)

PROFESSIONAL EXPERIENCE

Chronology Company Location Position Significant Accomplishments

Design and layout of Hall Effect

Honeywell Micro Staff

1973 1976 Freeport Ill LOHET II, ECKO IV, FY Series

Switch engineer

Proximity Switches.

Portable Products CMOS Design

Ft

Motorola Portable Lead, SCF, Signaling Decoder,

1976 1984 Lauderdale SMTS

Comm Advanced Development

Fla

Researcher

Chronology Company Location Position Significant Accomplishments

Design Manager for First in house

Design

1984 1986 BurrBrown/ TI Tucson Az CMOS Products include

Manager

MDAC7541A etc.

Design 6805 ASIC Division. CMOS

1986 1988 Motorola SPS Phoenix AZ. Manager Design Lead. .25u Standard Cell

/SMTS Library

Semiconductor Startup ~ Gate

MCE Semi West Palm

1988 1990 President Arrays ~ 200 Custom and Semi

Conductor Beach, Fla

Custom Ics.

Numerous Mixed serial Design

Principle Contributions in Seral Links

1990 1999 Intel Corp Chandler Az

Engineer Including USB2, Ethernet ~ 4 Chip

Set devices in Solano 815 SDRAM

COPEC/Advanced Portable Power

Longmont, Design Center Concentrating on

1999 2005 National Semi SMTS

Co PowerWiseTM Technology.

LM3230 CMOS RF Controller

Bangor Analog Power IC and MPU

on Chip regulators. Center of

Principle

2005 Present Intel Corp Chandler Az Excellence design Lead. Working

Engineer

on Massive Parallel Computing

Techniques.

MOST IMPORTANT CONTRIBUTIONS

1.) 1985 Motorola Tone Signaling zero crossing encoder/decoder (ESP/Shark Program) Modat, ZVEI etc.

First CMOS MPU (COSMAC) based decoder in a Motorola handheld radio.

Significance: Architect and Innovator together with Dave Muri, who radically changed

the direction of commercial Low Power Portable Electronics of the time; Transitioning from I2L (bipolar

technology) to CMOS using programmable microcontrollers for multi standard. Significantly, altered the course

of electronics at Motorola and the rest of the industry. The technique was used in Motorola s flagship handheld

MX Radio later in Saber Radio. Established Motorola as the clear leader in all aspects of portable

communications. Also awarded Motorola s first Microprocessor based Patent in the Handheld radio. (Patent

#4213185).This was an Industry first and used common hardware for both the encoder and decoder (all digital

zero crossing decoder approach).

2.) 1988 Manager and Sole designer of BurrBrowns (TI) first Precision 12 bit CMOS MDAC 7541A in 5u

CMOS

Significance: Significantly impacted trends in the adoption of CMOS technology for precision analog

products. Previous to this design, 12 bit guaranteed precision was not achievable in standard digital CMOS

Technology. The product stood the test of time and is still in production and is in the TI mixed signal data book.

(see technical publication #1)

3.) 1995 Intel s Lead Analog Designer Adopting Deep Submicron Analog CMOS technology for Serial Link

Communication on the CPU including USB2 and Ethernet on Motherboard and Solano SDRAM Design Lead.

Significance: Intel s analog capabilities were minimal and the pressure to integrated analog capabilities

onto the CPU and Chip Sets required significant modification of the design infrastructure (modeling, tools,

methodology). Intel being the #1 semiconductor supplier in the world, had the greatest impact on commercial

electronics. Integrating precision analog electronics was key to continued market leadership. Direct design

contributions were made by Jim Doyle to Ethernet 100Mbit, USB and USB2 serial ATA etc including the

integration of the first precision bandgap and subbandgap on Intel s products. These contributions enabled Intel

to retain the market leadership in Serial Link Communications on the Motherboard and Chip sets.. In addition,

Jim Doyle was the analog design lead for the SDRAM effort in a covert effort within Intel to backup Intel s stated

market position supporting RDRAM. The impact to the industry was estimated at >$10B. The success of Solano

and the 815/845 allowed Intel to regain market leadership in chip sets and memory interfaces markets. Also Jim

architected the first DDR interface using DLL technology on Intel Chip sets.

4.) 2001 National Semiconductor Analog Design Lead and COPEC Research Design Center Founder for

Powerwise Technology

Significance: Perhaps the most significant impact to National semiconductor s market direction and

image within the electronic sector. The impact is readily observed in the green initiative and National s stated

market direction and product support for PowerWiseTM technology. Jim was instrumental in setting up the ARM,

National, Artisan alliance for dynamic closed loop power supply control which is estimated in a savings >50%

over conventional dynamic voltage scaling . Jim recruited engineering team and was the senior design lead and

acting site technical manager. He designed the LM3230 CMOS PA controller for TriQuint Semiconductor which

was the highest margin product in National s portfolio. This also was the smallest lowest cost GSM EDGE

controller in the industry

5.) 2005 Intel s NBI Integrated Power Electronics and Massive Parallel Computing Initiative

Significance: NBI formed a integrated power initiative to reduce the cost of platform level

solutions in the ATOM or UMPC emerging handheld CPU market segments. Innovative ground breaking

techniques were developed including autonomous phase dropping, an industry first which maintains optimum

efficiency over all load conditions. Increase to battery life for handheld products incorporating this technology

was measured to be greater than 30%. The design was one of the most advanced power controllers in the

industry with advanced capabilities including power telemetry reporting, also boot strap startup which allows the

power supply controller to be run directly off of a high voltage battery supply with deep submicron processes

(>2X the breakdown). Most recently, Jim is the key technical lead on an NBI initiative to bring massive

biologically inspired parallel computing using FPGA and GPU technology.

Awards

1. Finalist EETimes 2004 EETimes Innovator of the Year for Contributions to Low Power Electronics.

2. 2004 10 Most Read and Download JSSC articles. (see publications)

3. Elected Senior Member of IEEE 2002 3.

4. Intel Division Recognition Award Intel for USB Contributions 12/18/97

5. MPG Innovator Day 1995 Finalist Intel New Concepts For Sub Micron ESD Protection

6. Intel Divisional Recognition Award Q1 1997 Assuming Responsibility Far Beyond Job Scope S

Parameter Characterization

7. Intel CEG Division Recognition Award for Contributions to GSM Baseband Processor. ACPT2

8. Intel NBI Division Recognition Award 2007 for Bangor Intel s First Integrated Power Regulator Product.

9. Invited Member of Intel's First Annual Technology Council Meeting 2000

10. Intel Division Recognition Award for Solano 815 Chip Set SDRAM FSB

11. Intel Division Recognition Award Camelot "Token Ring"

12. Intel Recognition Award for First Pass Success 82570 100Mbit Ethernet Chip

13. Intel Division Recognition Award Analog DSP Roadmap Q4 1998

14. Special Recognition for Technical Contributions to 3G (Intel Q3 2001)

15. Intel Division Recognition Award For excellent Teamwork in Preparing for bangor First Silicon Evaluation

of silicon functionality and outstanding Debug support: (Q2 2007)

16. Member National Register of Who's Who in Executives and Professionals 2004 2005

17. Finalist DEG Innovation Contest 2008 presenter Homogeneous Computing on Heterogeneous Systems .

18. Nominated Whos Who in America 2003 2005

19. SABA Motorola 1988

20. U.S. National Merit Scholar 1968

21. Renssalaer Award for Science Award for Science and Math Scholarship 1966

22. Miami Herald Runner Up for Silver Knight Award in Mathematics 1967.

23. University of Miami full Early Admission Full Scholarship for Science and Math 1968

24. NROTC Regular Full Scholarship University of Nebraska 1969. Navel Midshipmen Appointment. 1969.

Society Memberships (plus Invited Speaker)

1. Senior Member COMOC Denver Chapter. Invited speaker on CMOS Controller for EDGE PA s. 2003

2. Senior Member Phoenix Chapter IEEE Circuit Group. 2007.

3. Member FES (Florida Engineering Society) since 1982.

4. Member and Contributor to COPEC ( Colorado Power Electronics Center) since 2001.

5. Invited Speaker 2001: Professor Seth Sanders. Berkeley University Topic: Low Power Electronics

Techniques and National SemiConductor PowerWise Technology see Google James T Doyle

Berkeley.

6. Contributor, working group member and contributing author for IEEE 802.3,802.11 later International

Standard ISO8802.3 Listed in the author list..

7. Intel Neural network Rodeo 1995 Hosted by ASU and Intel. Televised Presentation on a Neural Network

Analog to Digital Techniques (Patent #6198421).

8. Numerous working group contributions to IEEE802.3 FDDI, 4T+ Phy and cable standards.

9. Invited Speaker Stanford University for Standards Convergence between Wired and Wireless 1996.

10. Professional Engineer, State of Florida, Active in Good standing since 1982 PE#24719

Committee Memberships

1. Active Reviewing Member since 2005 Intel Patent selection Committee for Circuits (Held Quarterly)

2. Invited PhD Defense Panelist for Prof Bertan, ASU and Prof Maksimovic University of Colorado.

3. Member of Intel's First Annual Technology Council Meeting 2000

4. SCR proposal reviewer and coordinator for several Universities (Ohio State, Iowa State, ASU

Berkeley.etc) for Intel Corporation.

5. Active IEEE Standards Committee Representative for Intel. 1995 2000. 803.3.x Standards (Involved in 5

standardization committees)

6. DEG Intel Senior Technologist Counsel (Grade 10 and Above) Member .weekly meetings for strategic

technology direction and Innovation Review.

7. Invited NASA Innovations Reviewer for Commercial Applications 2008

8. Intel Technical Investment Reviewer 1996. Responsible for technical review of Broadcom Startup

Investment. Directly worked with BroadCom on the100base4T+ design. Most profitable IPO in the history

of electronics.

Publications

1. James T. Doyle Design Considerations For High Precision CMOS Multiplying D/A Converters .

29th Midwest Symposium On Circuit And Systems. Editor Mohammed Ismail, Publisher: North Holland 1987

pp 5 11.

2. Contributor To Hall Effect Solid State Switches, Honeywell Corporation 1974

3. Motorola Corporation Numerous Internal Publications (Bound Books)

Topics Such As:

A. Low Noise Circuit Design by Jim Doyle

B. CMOS Subthreshold Circuit Design by Jim Doyle

C. Switched Capacities Circuit Design by Jim Doyle

4. Wrote And Validated Numerous Data Sheets For Motorola On Hand Held Radio.

Did A Radio Filing Data Book

5. Burr Brown Data Book, Data Sheet Application Note 7541A & 7545 MDAC. Listed in TI Mixed Signal Products

Data Book. (see TI Mixed Signal Products Data Book 2007 ).

6. Internal Publications At Honeywell. Eddy Current Killed Oscillator Design

Report 1974

7. S Parameter Characterization Of Oscillators by David Elting Intel Corp. 1993

I Was The Key Technical Contributor.

8. Contributed And Wrote CMOS DESIGN MANUAL At MCE Semiconductor

1988

9. New Concepts For SubMicron ESD Protection by James T. Doyle Intel Corp.

MPG S Innovator s Day 1995 Turning Ideas Into Reality Digest of Technical Papers March 30,1995 Santa

Clara, California pp13 17

10. Dae Woon Kang, Yong Bin Kim, and James T. Doyle, A High Efficiency Fully Digital Synchronous

Buck Converter Power Delivery System, IEEE Transactions on Very Large Scale Integration Systems,

vol.14, no.3, pp.229 240, March 2006.

11.Young Jun Lee, Dae Woon Kang, James T. Doyle, and Yong Bin Kim, A Sub 1V Power Supply Sub

bandgap with an Extended Voltage and Temperature Range, International SoC Design Conference,

pp.79 82, Oct. 2005.

12. Dae Woon Kang, James T. Doyle, Mark Hartman, Sandeep Dhar, Marty B. Dermody, Robert C. Woolf,

Ravindra S. Ambatipudi, and Yong Bin Kim, A Low Power Methodology for Portable Electronics, International

Symposium on Advanced Radio Technologies, pp.109 116, Mar. 2005.

13. James T Doyle, Y.B. Kim An Accurate DAC Modeling Technique Based on Wavelet Theory, CICC 2003 pg

11 15

14. James T Doyle, Y.B. Kim. D.W. Kang A CMOS Subbbandgap Reference Circuit With 1 Volt Power Supply

Voltage, IEEE JSSC Vol 31 no 1 Jan 2004 pp 252

15. James T Doyle, Fast and Accurate DAC modeling technique based on Wavelet Theory Microelectronics

Journal 35 2004 pp 451 460

16. Young Jun Lee Next Chip Solutions. Dae Woon Kang, National Semiconductor James Doyle National

Semiconductor Yong Bin Kim Northeastern University A Sub 1V Power Supply Sub bandgap with an

Extended Voltage and Temperature Range. http://www.ece.neu.edu/groups/hpvlsi/publication/Sub

1V_Bandgap_ISOCC.doc

17. Yong Bin Kim, Kyung Ki Kim, James T. Doyle: A CMOS Low Power Fully Digital Adaptive Power Delivery

System Based on Finite State Machine Control . ISCAS 2007: 1149 1152

18. J.T. Doyle, Wilsch, Young Jun Lee, and Y.Kim, Implementation of 1V Supply Voltage CMOS Subbandgap

Reference Circuit, IEEE International ASIC/SOC Conference, Sep 17 20, 2003 Portalnad,OR, pp.323 326

19.Yong Bin Kim and James Doyle, " A Low Power Digital Self Adjusting Adaptive Voltage Scaling System

Considering PVT and Loading Variations ", IEEE International Symposium on Circuits and Systems, New

Orleans, LA, May 27 30, 2007.

20.Yong Bin Kim and James Doyle, " A CMOS CORDIC Processor Design for Wireless Telecommunication ",

IEEE Midwest Symposium on Circuit and Systems(with NEWCAS), August 5 8, 2007, Montreal, Canada,

pp.1336 1339.

21.JSSC Articles Downloaded Most Often Most Read Recent JSSC Articles for 2004 posted May 6, 2005. THE

short list of IC design articels! these are the articles most often downloaded and serve as ...

sscs.org/jssc/hotreads04.htm 64k

22. EETimes Publicity.

http://www.eetimes.com/showArticle.jhtml?articleID=16505369

Small Gains in Power Efficiency now, Bigger Gains Tomorrrow

Jim Doyle SMTS, Bill Broach Manager

http://www.commsdesign.com/design_corner/showArticle.jhtml?articleID=16505370

http://miranda.hemscott.com/ir/cpx/pdf/Interim_Results_Presentation_2007.pdf

23.Upcoming Publications on VLSI Design. Topic: All Digital Closed Loop Voltage Scaling Technique.

Patents

1. U.S. Patent #7,453,244; James T. Doyle;

Low dropout regulator with control loop for avoiding hard saturation. [11/18/2008]

2. U.S. Patent #7,436,243; James T. Doyle, Dae Woon Kang;

Integrated circuits with on chip AC noise suppression. [10/14/2008]

3. U.S. Patent #7,253,598; James T. Doyle, Dae Woon Kang, Martin Dermody;

Bandgap reference designs with stacked diodes, integrated current source and integrated sub bandgap

reference. [8/7/2007]

4. U.S. Patent #7,248,080; James T. Doyle;

Power supply switching at circuit block level to reduce integrated circuit input leakage currents. [7/24/2007]

5. U.S. Patent #7,170,269; James T. Doyle;

Low dropout regulator with control loop for avoiding hard saturation. [1/30/2007]

6. U.S. Patent #6,927,619; James T. Doyle;

Method and system for reducing leakage current in integrated circuits using adaptively adjusted source voltages.

[8/9/2005]

7. U.S. Patent #6,914,487; James T. Doyle, Dragan Maksimovic, Yushan Li;

Method and system for providing power management in a radio frequency power amplifier using adaptive

envelope tracking. [7/5/2005]

8. U.S. Patent #6,900,697; James T. Doyle, Dragan Maksimovic, Yushan Li;

Method and system for providing power management in a radio frequency power amplifier by dynamically

adjusting supply and bias conditions. [5/31/2005]

9. U.S. Patent #6,771,101; James T. Doyle;

CMOS reference circuit using field effect transistors in lieu of resistors and diodes. [8/3/2004]

10. U.S. Patent #6,629,254; Syed R. Naqvi, James T. Doyle;

Clocking architecture to compensate a delay introduced by a signal buffer. [9/30/2003]

11. U.S. Patent #6,617,836; James T. Doyle, Yushan Li;

CMOS sub bandgap reference with an operating supply voltage less than the bandgap. [9/9/2003]

12. U.S. Patent #6,323,674; Udbhava A. Shrivastava, James T. Doyle, Edward J. Bawolek;

Technique and apparatus for terminating a transmission line. [11/27/2001]

13. U.S. Patent #6,281,743; James T. Doyle;

Low supply voltage sub bandgap reference circuit. [8/28/2001]

14. U.S. Patent #6,198,421; James T. Doyle, Carl F. Liepold;

Neural flash analog to digital converter using weighted current similation. [3/6/2001]

15. U.S. Patent #6,184,739; James T. Doyle;

Advanced near ideal mixer. [2/6/2001]

16. U.S. Patent #6,147,548; James T. Doyle;

Sub bandgap reference using a switched capacitor averaging circuit. [11/14/2000]

17. U.S. Patent #6,107,819; James T. Doyle;

Universal non volatile logic gate. [8/22/2000]

18. U.S. Patent #6,084,537; Steven P. Hardy, James T. Doyle;

Return to zero transmitter. [7/4/2000]

19. U.S. Patent #6,081,139; Carl F. Liepold, James T. Doyle;

Differential amplifier with lateral bipolar transistor. [6/27/2000]

20. U.S. Patent #6,075,407; James T. Doyle;

Low power digital CMOS compatible bandgap reference. [6/13/2000]

21. U.S. Patent #6,069,503; James T. Doyle;

High value FET resistors on a submicron MOS technology. [5/30/2000]

22. U.S. Patent #6,052,020; James T. Doyle;

Low supply voltage sub bandgap reference. [4/18/2000]

23. U.S. Patent #6,009,124; James P. Smith, James T. Doyle;

High data rate communications network employing an adaptive sectored antenna. [12/28/1999]

24. U.S. Patent #5,942,995; Steven P. Hardy, James T. Doyle;

Return to zero receiver. [8/24/1999]

25. U.S. Patent #5,856,980; James T. Doyle;

Baseband encoding method and apparatus for increasing the transmission rate over a communication medium.

[1/5/1999]

26. U.S. Patent #5,841,821; James T. Doyle, Carl F. Liepold;

Bi directional low pass filtering method and apparatus. [11/24/1998]

27. U.S. Patent #5,717,716; James T. Doyle;

Quasi adaptive analog equalization method and apparatus. [2/10/1998]

28. U.S. Patent #5,694,439; James T. Doyle, Carl F. Liepold;

Bi directional low pass filtering method and apparatus. [12/2/1997]

29. U.S. Patent #5,408,235; James T. Doyle, Tim Beatty, Carl F. Liepold;

Second order Sigma Delta based analog to digital converter having superior analog components and having a

programmable comb filter coupled to the digital signal processor. [4/18/1995]

30. U.S. Patent #5,374,859; James T. Doyle, Yong Bin Kim;

Low power dual power supply high resolution comparator. [12/20/1994]

31. U.S. Patent #5,202,590; Carl F. Liepold, James T. Doyle;

Subthreshold sense circuit for clamping an injected current. [4/13/1993]

32. U.S. Patent #4,845,444; James T. Doyle;

Frequency doubling crystal oscillator via a current mirror. [7/4/1989]

33. U.S. Patent #4,835,487; James T. Doyle, Bart R. McDaniel;

MOS voltage to current converter. [5/30/1989]

34. U.S. Patent #4,717,836; James T. Doyle;

CMOS input level shifting circuit with temperature compensating n channel field effect transistor structure.

[1/5/1988]

35. U.S. Patent #4,646,427; James T. Doyle;

Method of electrically adjusting the zener knee of a lateral polysilicon zener diode. [3/3/1987]

36. U.S. Patent #4,213,185; David L. Muri, James T. Doyle;

Microprocessor tone synthesizer with reduced quantization error. [5/15/1980]

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