Engineer Manager

Rafael J. Betancourt-Zamora

********@******.********.*** 650-***-**** Silicon Valley, CA

PROFESSIONAL SUMMARY

A people-oriented IC Design Manager/Architect with over twenty four (24) years of

digital/analog CMOS IC Design experience. Completed over 25 tapeouts. Experienced in

complete product development lifecycle, from initial conception through design,

verification, fabrication & testing. Driven by project success and the success of the team.

WORK HISTORY

March 2002 to present, Synaptics, Inc., Santa Clara, CA

For this leading manufacturer of human interface sensing devices serves as follows:

Principal Silicon Architect, Touch (9/11 to Present)

Silicon development technical lead for Touchscreen CMOS controllers for mobile, tablet, and notebook PC

applications. Oversee the technical aspects of silicon project definition and execution combining broad technical

skills, technical lead skills and people skills to oversee a talented interdisciplinary design team. Also interact with

internal departments such as Strategic Marketing and Business Units as well as external customers to help shape

Synaptics future core technologies.

Sr. Analog Mixed-Signal Design Manager (6/10 to 9/11), responsible for a team of 10 engineers.

IC Design Manager, Advanced Development Group (10/09 to 6/10), responsible for a team of 3 engineers.

System Silicon Design Manager (9/05 to 10/09), responsible for a team of 10 engineers.

Started with Synaptics just after IPO ($100M revenue, $55M market cap) and managed through 30%+ year over

year growth for the last 10 years (FY11 $598M revenue, about $1B market cap). My contributions were

instrumental to the company s growth as detailed below:

From June 2010 through September 2011, assumed management for focused Analog Mixed-signal team of

6 people that grew up to 10 full-time IC Designers (both full-time permanent and contractors) .

Managed (functional and /or project) every significant Synaptics silicon development over the last 7 years

deployed in the majority of the current products (OneTouch, Series-2000, Series-3000/3200, Series

7000/7300). These chips have been used in hundreds of millions of notebook PCs (e.g., HP, Dell, Lenovo)

and tens of millions of MP3 players (iPod, MS Zune, Creative, Samsung), mobile phones (e.g. Samsung, LG,

Nokia), smart phones (Nokia, Sony-Ericsson, HTC, RIM's Blackberry), tablets (TBA) and other intelligent

devices (Logitech Squeezebox/Mice/Keyboards, Sony LCD TV).

Managed the Analog Mixed-signal CMOS design team (of 4 to 10 full-time IC designers) that developed and

released all current Synaptics low-power, low-cost capacitive sensing ASICs for human interface

applications (e.g., TouchPad and TouchScreens). Started as manager of all ASIC Design (Digital, Analog &

Mixed-signal), and grew the team through multiple reorganizations from 4 up to 10 full-time IC designers.

Managed successfully the definition/specification for advanced mixed-signal capacitive sensing ASICs,

including silicon roadmap (new project definition, MRD/PRD), technology scoping and feasibility (technical

risks, make vs. buy decisions) for every silicon development released to production in the last 7 years.

Collaborated in defining product requirements by interfacing with Marketing, Systems Engineering,

Applications, Software, and other internal customers; we produced 7 product requirement documents and

of these, 5 were released to production, on-time, within budget, and meeting all performance requirements.

Representative to the IP committee, 1 patent (U.S. Pat. No. 8,058,884 issued November 15, 2011).

Managed contractors (NDA, negotiated and wrote contracts, managed progress).

Performed in-house training for FAEs, managed external customer requests from the field.

Negotiated with third-party IP vendors as well as silicon foundries.

www.betasoft.org Rev. 2012-01-29, 1/4

Rafael J. Betancourt-Zamora

********@******.********.*** 650-***-**** Silicon Valley, CA

WORK HISTORY (CONT'D)

Synaptics, Inc., Santa Clara, CA. Senior Analog IC Design Engineer (8/03 8/05)

Technical lead responsible for project management; supervised and mentored 4 junior designers and 2

layout / mask design contractors. As technical lead for T1006 and T1007 Touch Controller ASICs, I was

responsible for the design and release to production of ASICs that have shipped 100s of millions of units

and are embedded in about 70% of all notebook computers made worldwide.

Designed analog circuits for low-power, low-cost capacitive (T1006/7) & resistive (T1100) sensing ASICs.

Designed low-power oscillators and interfaced with layout contractor for post-layout verification.

Technical representative to the Mobile Advisory Council and Trusted Computing Group.

Synaptics, Inc., Santa Clara, CA. Senior Analog IC Design Contractor (3/02 8/03)

Designed analog circuits for low-power, low-cost capacitive and resistive sensing ASICs.

Designed low-power oscillators and interfaced with layout contractor for post-layout verification.

Jul 1999 to Oct 2001, Innovative Semiconductors, Inc., Mountain View, CA.

Sr. Mixed-signal IC Design Engineer

USB 2.0 PHY IP:

Designed 480Mb/s analog transceivers for USB 2.0 including cable driver, receiver, squelch detector, and

clock recovery DLL in TSMC s 0.25um and 0.18um CMOS processes.

Wrote specifications for 480MHz PLL clock synthesizer and interfaced with PLL design contractor for post-

layout verification and performance characterization.

IEEE-1394 PHY IP:

The 1394 PHY IP project in which I performed script development and performed analog verification,

bench testing, trouble-shooting and characterization, assisted with DRC and LVS ( TSMC 0.35um CMOS) as

well as porting to UMC s 0.18um CMOS, was released to production, on-time, within budget, and met

performance specifications.

Performed analog verification of 400Mb/s serial transceiver PHY using Mentor s Accusim simulator.

Developed scripts in AMPLE to automate analog verification (PVT).

While pursuing a graduate degree in EE at Stanford (1990-2005), actively involved in technology

consulting, participating in the conception, development and evaluation of several electronic products

(dates may overlap based on consulting with multiple clients at the same time).

7/97 10/98, Pennie & Edmonds, LLP, Palo Alto, CA. IC Design Consultant.

Analyzed technical patents for infringement, and reviewed technical documents to elucidate and explain

operation of complex digital ICs to legal staff.

Worked closely with attorneys to prepare for patent application filing and infringement litigation.

Specialized in all aspects of digital ASIC intellectual property.

7/96 5/99, Eisenlohr Technologies, Inc., Davis, CA. Hardware Design Consultant for X-Caliper Project.

Participated in all aspects of product development and designed the hardware (all digital, analog and

power supply circuits) for X-Caliper, a portable battery-operated instrument used to perform precise

measurements of dimensions and angles on X-ray films; over 1,000 units of X-Caliper were sold world-wide

to orthopedic surgeons, hospitals, clinics, medical research centers, and manufacturers of orthopedic

implants (hip, knee, etc.).

Design was based on 68HC11, custom LCD s, keypad, EL-backlighting, and triple regulated power supplies

running off three AA batteries.

Incorporated into X-Caliper a novel inclinometer circuit based on MEMs accelerometers.

www.betasoft.org Rev. 2012-01-29, 2/4

Rafael J. Betancourt-Zamora

********@******.********.*** 650-***-**** Silicon Valley, CA

WORK HISTORY (CONT'D)

1/96 3/97, Jefferson Laboratories, Inc., Palo Alto, CA. RF Engineer.

Fabricated prototypes, tested, and performed experimental research in antennas for biotelemetry under a

NASA contract.

Developed experimental technique for measuring performance of implantable telemetry link.

Performed modeling of electrically short loop antennas for biotelemetry.

Member of the team which developed biotelemetry antennas for the Rodent Advanced Flight Habitat

(RAHF) flown in the Space Shuttle in May 1998.

9/94 12/95, SmartPad, Inc., San Francisco, CA. Hardware Design Consultant.

Designed a portable battery-operated, x86 processor-based, embedded MS-DOS laptop computer

(PowerPad) for educational use.

Designed all digital, analog and power supply circuits for the PowerPad product.

Participated in all aspects of PowerPad product development including product definition, circuit design,

prototyping, integration, assembly language programming, and BIOS/DOS configuration and

troubleshooting.

6/93 10/93, Sun Microsystems Inc., Sunnyvale, CA. Architecture Verification Engineer.

Verified the architecture of the UltraSPARC V.9 64-bit superscalar processor.

Defined and implemented Architecture Verification to certify compliance with the SPARC V.9 specification.

6/92 9/92, Silicon Graphics Inc., Mountain View, CA. Digital Verification Engineer.

Verified functionality of a high-performance 80K-gates I/O-DMA controller gate array.

Assisted with prototype development and debugging of the R4400-based Onyx RISC multiprocessing

graphics workstation.

6/91 12/91, Intel Corp., Santa Clara, CA. Micro-architecture Verification Engineer.

Verified the architecture of the Pentium processor using Quickturn s Rapid Prototyping System.

Implemented and debugged Pentium s caches using Quickturn s RPMs.

Designed and built a Pentium prototype that ran successfully MS-DOS, Windows, UNIX and various

applications in a PC environment.

7/87 9/90, Hughes Aircraft Company, Electro-Optical & Data Systems Group, El Segundo, CA.

Member of the Technical Staff, MTS-I.

Performed the physical design and verification of a 5.2K-gates (41k transistors) 160MHz image processing

chip (FIR filter) using Bell Labs GaAs HEMT technology.

EDUCATION

Rigorous academic training in CMOS integrated circuit design

2005 Engineers in Electrical Engineering (D. Eng.), Stanford University, Stanford, CA

Emphasis in Circuits, Architecture, VLSI & low-power CMOS radio frequency circuits. Additional

courses in Engineering Management, Entrepreneurship, and Intellectual Property Law. Designed,

built, and tested analog instrumentation for biopotential recordings from implantable

microelectrode array neural interface. Supervised independent research of Masters students in PLL

design, low-power ADC and low-power RF.

Thesis: Injection-locked ring oscillator frequency dividers. Advisor: Thomas H. Lee

www.betasoft.org Rev. 2012-01-29, 3/4

Rafael J. Betancourt-Zamora

********@******.********.*** 650-***-**** Silicon Valley, CA

EDUCATION (CONT'D)

1989 MSEE, University of Southern California, Los Angeles, CA. Specialized in analog and digital IC design.

1987 BSEE, University of Puerto Rico, Mayag ez, Puerto Rico. Completed a 5-year program in 4 years.

Graduated magna cum laude with a specialization in electronics. GPA: 3.75/4.00.

CONTINUING EDUCATION

Professional training in CMOS, mixed-signal & RF circuits, and Leadership / Management

Synaptics Leadership Development Forum, Los Gatos, CA, June 2010.

Advanced Microsoft Project Training, Santa Clara, CA, December 2009.

Kepner-Tregoe Decision Analysis, Santa Clara, CA, October 2008.

Leadership Development Program, Center for Creative Leadership, San Diego, CA, August 2007.

RF IC Design for Wireless Communication Systems, MEAD Microelectronics, Inc., San Francisco, CA,

April 22-26, 1996.

Practical Aspects of Analog & Mixed-mode IC Design, Oregon Center for Advanced Technology

Education, Portland State University, Portland, Oregon, July 10-14, 1995.

SELECTED PUBLICATIONS

System and method for measuring a capacitance and selectively activating an indicating

transducer, U.S. patent 8,058,884 (issued November 15, 2011).

1-GHz and 2.8-GHz CMOS Injection-locked Ring Oscillator Prescalers, Symposium on VLSI Circuits,

June 14-16, 2001, Kyoto, Japan.

CMOS VCOs for Frequency Synthesis in Wireless Biotelemetry, International Symposium on Low Power

Electronics and Design, August 10-12, 1998, Monterey, California.

A 1.5mW, 200MHz CMOS VCO for Wireless Biotelemetry, First International Workshop on Design of

Mixed-Mode Integrated Circuits and Applications, July 28-30, 1997, Cancun, Mexico.

ENGINEERING TOOLS, LANGUAGES, AND OTHER SKILLS

CAD: Cadence (Spectre, Spectre RF, Analog Artist, Virtuoso, AMS Designer) & Mentor Graphics (Design

Architect, Accusim/ELDO, IC Station), Verilog, Verilog-AMS, HSpice

Languages: C, C++, Assembly; AMPLE (Mentor), Skill/OCEAN (Cadence), some Perl

PROFESSIONAL AWARDS & SCHOLARSHIPS

NASA-Ames Research Center ; Graduate Training Grant 1995-98

National Consortium for Educational Access, Inc. Fellowship, 1994-97

General Electric Foundation; Faculty for the Future Fellowship 1993-94

Hughes Masters Fellowship; 1987-89

PROFESSIONAL MEMBERSHIPS & AFFILIATIONS

Senior Member of the Institute of Electrical and Electronics Engineers (IEEE)

IEEE Solid-state Circuits Society

IEEE Circuits & Systems Society; Reviewer for TCAS-I and TCAS-II Journals

Tau Beta Pi Engineering Honor Society

Phi Kappa Phi National Honor Society

www.betasoft.org Rev. 2012-01-29, 4/4

Contact this candidate