Design Process

BASAB DATTA

(Tel) +1-413-***-****

** *** *********** ****

(Fax) +1-413-***-****

Apartment # 90

Amherst, MA 01002 (home) http://www-unix.ecs.umass.edu/~bdatta

******@***.*****.***

***, ******* *ngineering Building

University of Massachusetts-Amherst (office)

Objective

To obtain a challenging industrial position in the area of digital full-custom/semi-custom circuit design

Research Interests

PVT-tolerant circuit design techniques, low-power digital circuit design, novel circuit techniques for digital,

low power and high resolution thermal sensing, statistical process-variability analysis of CMOS circuits,

sensor calibration, droop/temperature/NBTI effects on deep-sub-micron VLSI circuits, design of low-power

process-monitoring circuits, low-power memory circuits, reliability (NBTI) monitoring circuits, low power

interconnect design, electro-thermal modeling of multi-level interconnects

Education

PhD in Electrical and Computer Engineering (since Fall 2007, CGPA: 3.86) Expected: Dec 2010

Thesis Title: Temperature Effects and On-Chip Thermal Sensing in Deep Sub-Micron CMOS

M.S. in Electrical and Computer Engineering September 2007

University of Massachusetts Amherst, Amherst, MA (CGPA: 3.77)

Graduate Course-work: VLSI Design Principles, VLSI testing and verification, Analog CMOS IC

design, Reconfigurable Computing, Design for manufacturability and reliability of VLSI circuits, VLSI

Design Project, Computer Architecture, Communication & Signal Processing, Physics of

Semiconductor Devices, Computer Algorithms, Optimal Control Theory, Probability & Random

Processes

B-Tech in Electronics and Communications Engineering May 2005

G.G.S. Indraprastha University, New Delhi, India (Aggregate: 81.2%)

Relevant courses: Computer Architecture & Organization, Electromagnetic field theory, Digital

Circuits & Systems, Analog Electronics, Microprocessors (I & II) Computer Networks, Mobile

Computing, Embedded Systems, Antennas & Wave Propagation, Telecommunication Networks,

Digital Signal Processing, Digital Image Processing, Operating Systems, Control Systems .

Industrial Experience

(Fall 2007) Co-op at Advanced Micro Devices, Sunnyvale, CA (Mentor: Dr. Rich Klein)

- Involved in the design of a 32nm test-chip in Silicon-on-Insulator (SOI) process. Designed thermal

sensors and measurement circuits for on-chip thermal profiling. Designed (with mask specifications)

different variants of performance ring-oscillators to study effect of beta-ratio, dummy poly-sizing,

contact spacing, number of contacts, circuit topology on circuit-performance in 32nm process

technology.

Academic Experience

-

(Since Summer 2006) Graduate Research Assistant: VLSI Circuits & Systems Group

Advisor: Prof. Wayne P. Burleson

Circuits for Accurate Thermal Management (SRC funded, Task 1415.001)

Thesis research focuses on design, integration and implementation of novel, digital on-chip thermal

sensing schemes in nanometer CMOS.

- Thermal Sensing Circuits [1][2][3][4][5][6][9][10][15][17][18][19]

Design of a low-power, process-variation tolerant, track and hold based sub-threshold thermal

sensor capable of providing a high resolution of

proposed high-sensitivity sub-threshold thermal sensor using 45nm IBM-SOI models (to be

fabricated by MOSIS). Taped out test-chip in July 2010.

Design of a thermal sensing scheme for Content Addressable Memory Circuits.

Design of an Interconnect-based oscillator for Thermal Sensing (IBOTS) to perform thermal sensing

at both substrate level and interconnect level and generate full 3-D thermal map. Studied effects of

PV-variability on sensor response and proposed mitigation techniques.

Design of a thermal sensing scheme based on wires (ThermoWire) to estimate both horizontal and

vertical gradients in 45nm technology.

Study of process-impact on the 2-point calibration model used for on-chip thermal sensors and

mitigation approaches.

Detailed analysis of differential ring oscillator based thermal sensing. Survey of existing digital

thermal sensing techniques at the circuit level.

- Temperature Effects on Deep Sub-Micron Circuit Design: super and sub-threshold [8][10][17]

Study of temperature effects on Sub-Threshold circuit design: thermal impact on variability metrics

current, delay, energy, static noise margin and the resultant impact on circuit-design choices:

device-sizing, logic-depth, fan-out & beta-ratio, sub-threshold energy optimization in the presence of

wire-loading

Study of thermal impact on on-chip CMOS logic (super-threshold), memory and interconnect.

Design of temperature insensitive circuits in deep sub-micron CMOS.

- On-Chip Process/Reliability/Droop Monitoring [11][12][13][14][16][20]

Design of a novel, high-sensitivity process-sensor utilizing sub-threshold operation. Development of

an algorithm to perform process-tolerant calibration of on-chip thermal sensors. Designed and

implemented test-chip of proposed process-sensor using 45nm IBM-SOI models. Taped out test-

chip in July 2010.

Development of circuit-level NBTI macro-models to perform online, collaborative reliability

monitoring using on-chip PVT sensors. Design of an NBTI detector to measure device-aging. Studied

NBTI effects on repeater-based global interconnect performance.

Study of thermal impact on voltage-droop caused by on-die activity.

- Heat Removal using Physical Features [7]

FEM thermal simulations to study and quantify temperature planarization effect of Copper

Dummy-Fills (used in CMP process) in 45nm technology for multi-level interconnects.

Publications & White Papers*

[1] T.Wolf*, S.Mao*, D.Kumar*, B.Datta*, W.Burleson* and G.Gogniat+ Collaborative monitors for

Embedded System Security, First Workshop on Embedded System Security, Seoul, September 2006

* Department of Electrical and Computer Engineering, University of Massachusetts-Amherst, USA

+ Laboratory LESTER, University of South Britanny, Lorient, France

[2] B.Datta, W.Burleson Low Power and Robust On-Chip Thermal Sensing using Differential Ring

Oscillators, 50th IEEE Mid-West Symposium on Circuits and Systems (MWSCAS), August 2007,

Montreal

[3] B.Datta, W.Burleson Low Power On-Chip Thermal Sensing based on Wires, IEEE International

Symposium on VLSI System-on-Chip (VLSI-SoC), October 2007, Atlanta

[4]* B.Datta, W.Burleson Innovative Techniques for On-Chip Thermal Sensing in Deep-Sub-Micron

CMOS, SRC TECHCON, 2007

[5] B.Datta, W.Burleson Collaborative Sensing of On-Chip Wire Temperatures using Interconnect

based Ring Oscillators, ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2008, Orlando

[6] B.Datta, W.Burleson Temperature Measurement in Content Addressable Memory Cells using

Bias Controlled VCO, IEEE International System-On-Chip Conference (SOCC), October 2008,

Newport Beach

[7] B.Datta, W.Burleson On Temperature Planarization effect of Copper Dummy Fills in Deep

Nanometer Technology, IEEE International Symposium on Quality Electronic Design (ISQED), 2009,

San Jose

[8] B.Datta, W.Burleson Temperature Effects on Energy Optimization in Sub-Threshold Circuit

Design, IEEE International Symposium on Quality Electronic Design (ISQED), 2009, San Jose

[9] B.Datta, W.Burleson Low-Power, Process-Variation Tolerant On-Chip Thermal Monitoring using

Track and Hold Based Thermal Sensors, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2009,

Boston

[10]* B.Datta, W.Burleson Temperature Effects in Sub-Threshold and Thermal Sensing in Sub-

Threshold, SRC TECHCON, 2009

[11] B.Datta, W.Burleson Calibration of On-Chip Thermal Sensors using Process Monitoring

Circuits, IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, 2010

[12] B.Datta, W.Burleson Circuit-level NBTI Macro-Models for Collaborative Reliability Monitoring,

ACM Great Lakes Symposium on VLSI (GLSVLSI), Providence, 2010

[13] J.Zhao, B.Datta, R.Tessier and W.Burleson Multi-Core Thermal Aware Adaptive Voltage Droop

Compensation, ACM Great Lakes Symposium on VLSI (GLSVLSI), Providence, 2010

[14] B.Datta, W.Burleson Analysis and Mitigation of NBTI Impact on PVT Variability in Global

Interconnect Performance, ACM Great Lakes Symposium on VLSI (GLSVLI), Providence, 2010

[15] B.Datta, W.Burleson A 12.4 2 133.4 W 4.56mv/ C Resolution Digital On-Chip Thermal

Sensor in 45nm CMOS Utilizing Sub-Threshold Operation, submitted at IEEE International

Symposium on Quality Electronic Design, 2011

[16] B.Datta, W.Burleson - A 45.6 2 13.4 W 7.1V/V Resolution Sub-Threshold Based Digital Process

Sensor in 45nm CMOS, submitted at Design Automation and Test in Europe (DATE), 2011

[17] B.Datta, W.Burleson Thermal Impact on Energy Optimization in Sub-Threshold Circuits in

Deep Nanometer Technologies, submitted at Journal of Low Power Electronics, 2010

[18] B.Datta, W.Burleson On-Chip Thermal Sensing using Wires and Interconnect Based Ring

Oscillators, submitted at Analog Integrated Circuits and Signal Processing (Springer), 2010

[19] B.Datta, W.Burleson A High-Sensitivity and Process-Tolerant Thermal Sensing System in Deep

Sub-Micron CMOS, in preparation, IEEE Transactions on VLSI (TVLSI), 2010

[20] B.Datta, W.Burleson A High-Sensitivity Process Sensor in 45nm CMOS Utilizing Sub-

Threshold Operation, in preparation, IEEE Transactions on Circuits and Systems (TCAS-II), 2010

Course Projects

(Spring 2008) Monte Carlo Simulation to study carrier transport in p-n junction: Applied the

Monte-Carlo technique to study the carrier transport problem in p-n junctions

(Fall 2006) Cache Simulator to perform energy & temperature comparisons of different

Instruction-Cache configurations: focused our analysis on the energy and temperature

characteristics of different cache configurations in the embedded processor domain; evaluating 2

novel I-Cache designs Filter Cache and HotSpot Cache

(Spring 2006) Implementation of an access-count-based Dynamic Thermal Management

scheme on an architectural simulator - SIMPLESCALAR : Power measures from a power

simulator WATTCH and temperature values generated by HOTSPOT ( chip temperature modeling

tool) were integrated to develop an algorithm that predicts local hotspot creation based on a run-time

access/invocation rate of individual resource units (with optimal performance penalty).

(Spring 2006) Study of capacitance impact of dummy-fills (used in Chemical Mechanical

Polishing ) in 65nm case study of C17 benchmark : Analysis was performed using the

Synopsys Modeling tool Raphael for both 65nm and 90nm technology nodes.

(Spring 2006) Design of a Digital Image Watermarking System for both FPGA and Standard

Cell Implementation: The watermarking encoder and decoder were coded in Verilog. Functional

verification was performed using ModelSim SE 6.0. Power, area and timing analysis was performed

for the individual blocks. The Synopsys tools Design Compiler and Design Analyzer were used for

performing the Standard Cell based analysis.

(Fall 2005) Analysis of a ring oscillator based on-chip thermal sensor in 65nm technology:

Analyzed a ring oscillator in 65 nanometer technology using the Berkeley Predictive Technology

Models and determined its frequency dependence on temperature, supply voltage noise sensitivity,

immunity to manufacturing process variations using Monte Carlo analysis

(Fall 2005) File format conversion of digital benchmark circuits using a parser and lexical

analyzer for fault simulation: Developed the parser in YACC (compiled by BISON) and compiled the

LEX file using FLEX to convert a set of ISCAS combinational benchmark circuits into a specific

format suitable for fault simulation and diagnosis.

(Fall 2005) Design of a telescopic operational amplifier for a given set of design specifications:

Design constraints included the Gain, Bandwidth, Phase Margin, Slew rate, Output voltage swing,

power consumption. Design corroborated through simulations run on Analog Design Environment

(Cadence).

Teaching Experience

Fall 2006: Teaching Assistant for the course ECE 558: Introduction to VLSI Design

Fall 2009: Teaching Assistant for the course ECE 568: Computer Architecture

Spring 2010: Teaching Assistant for the course ECE 559: Advance VLSI Design

Technical Skills

EDA Tools: Virtuoso (Cadence) Design Suite, Cadence Schematic editor, Cadence Layout editor, Spectre,

IRSIM, Synopsys- HSPICE, Rapahel, Design Analyzer, Design Compiler and PrimeTime

Programming Languages: C, C++, Verilog HDL, VHDL.

OS: UNIX, Linux and Windows.

Packages: MS Office, Xilinx FPGA design suite, Altera Quartus II Software Suite

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