Project Manager Engineer

Sharlin Fang

Email: ***********@*****.***

Personal home page: http://www.reocities.com/PROFESSIONAL

EXPERIENCE

Magma Design Automation, Cupertino,

CA Oct. 2000 to 2001

Design Engineer, Department of Operations: Assurance the quality of Blast

tool. Test flow and repeatibility. Put design into QOR suite. Use Tcl scripts

to automate a design flow.

Acer Semiconductor America, Cupertino, CA

Feb. 1999 to Oct.1999

Project Manager. Design Services: Provide help on layout editor installation,

automation and DRC and LVS design rules implementation and verification.

Foundry services: Interface with and support customers and design engineers

on back end design issues.

Cadence Design Systems Inc., San Jose, CA

Aug. 1998 to Feb. 1999

Sr. Member of Technical Staff. Virtuoso layout tool automation: Validated

and maintained Virtuoso layout editor and layout flow. Tool used: IC craftsman,

Device level editor and router, Dracula and Diva verification tools.

S3 Inc., Santa Clara, CA Sept. 1997 to Aug.

1998

Member of Technical Staff. Embedded DRAM Design: Designed and maintained

integrated DRAM used for Mobile graphic accelerator, full chip simulation

and verification using TimeMill Tool, Hspice simulation, ViewLogic waveform

analysis and debug. Layout Supervision and Verification: Supervised layout

designers on layout modifications and created LVS and Dracula DRC rule

files for verification.

Project completed: 16kx128 bank integrated DRAM used in S3 Mobile chip.

Mosel Vitelic, San Jose, CA Aug. 1994 to Aug.

1997

Design Engineer. Participated in memory development in both volatile (DRAM)

and nonvolatile (Voice ROM) memory. Designed and analyzed EDO and FP Mode

DRAM with duties including schematic entry, HSPICE simulation, netlist

extraction, layout planning and supervision, DRC, LVS and Dracula verifications.

Projects completed: 1Mx8, 512Kx16, 256Kx32 EDO DRAM.

LeadingWay, Irvine, CA May 1992 to August

1992

Programmer. Developed and Maintained LeadingWay Transaction Shells, a multimedia

software development system for education and training.SKILLS

Languages: Tcl, PERL VHDL, Verilog HDL, SKILL, C, HTML, 68000

Assembly

Systems: UNIX, SUN, SPARC, MS-DOS, Windows

Applications: HSPICE, Cadence OPUS and EDGE layout tools, PDRACULA, Viewlogic

Powerview simulation tool, Synopsys EPIC TimeMill simulation and chip synthesis

tool, library-tech cell characterization tool, ECS, MATLAB, Word processor.EDUCATION

University of Southern California, Los Angeles, CA Aug. 1993

to June 1994

M.S. Electrical Engineering

University of British Columbia, British Columbia, Canada Aug. 1989 to June

1993

B.S. Electrical EngineeringACTIVITIES/AWARDS/PATENTS

MicroSoft Certified System Engineer (MCSE

+ Internet) 2000, certification granted in May, 2000.

US

Patent # 5,889,414 Programmable circuits 1997, March 30, 1999

US

Patent # 5,841,718 Use of voltage equalization in signal-sensing circuits,

Nov. 24, 1998

Extra Effort Award form MOSEL VITELIC, Q1 and Q4 1996

Member, IEEE, 1990-1997

Member, Society of Women Engineers, 1993-1994

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