Engineer Design
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Title:JOHN NIEZNANSKI
abp58d@r.postjobfree.com
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NAME: JOHN NIEZNANSKI
ADDRESS:
CITY: Pittsford
STATE/PROVINCE: FL
ZIP/POSTAL CODE: 33511
COUNTRY: USA
EMAIL: abp58d@r.postjobfree.com
PHONE: 716-***-****
CANDIDATE ID: N/A
CITIZENSHIP: US
Citizen
EDUCATION: Not Entered
EXPERIENCE: Not Entered
WILL RELOCATE: Not Entered
RELOCATION INFO: Not Entered
JOB WANTED: Not Entered
HOMEPAGE:
COMMENTS:
HOTSKILLS:
ESUME
JOHN A. NIEZNANSKI
10 Mill Valley Rd.
Pittsford, NY 14534
abp58d@r.postjobfree.com
http://home.att.net/~nieznanski10 Mill Valley Rd.
Pittsford, NY 14534 January 28, 1998
abp58d@r.postjobfree.com
http://home.att.net/~nieznanski
Dear Engineering Professional:
I am writing to you in regards to our mutual interest in developing
timely and cost effective electronic design, test and packaging
solutions demanded by our current clients and future customers.
We both recognize that there are many opportunities in today's
marketplace for those organizations and individuals who can
successfully master the numerous design, test and packaging technology
options to deliver consistently high quality solutions to rigorous
customer requirements. We recognize that our clients and customers
want solutions which are correct by design, delivered on time, right
the first time, each and every time. We recognize that the best
strategy for long term business success is uncompromised customer
satisfaction.
I can help you fill your customers needs now. If you represent one of
those organizations which has an interest in the areas mentioned
above, I will be glad to show you how I can help.
As you are no doubt aware, virtually all electronic products and
sub-assemblies are being designed to deliver more functionality, in
less space, in less time and at less cost than ever before. These
drivers apply across the application spectrum from low cost, high
volume systems to low-mid volume, high value systems. Furthermore,
these forces apply across all market segments and serve as the
underlying growth engine and catalyst that fuels not only the
electronic industry in particular, but many dependent industries
utilizing embedded electronics. Leading organizations leverage these
forces to provide a competitive advantage in the marketplace.
Nevertheless, escalating competitive pressures both locally and
globally mandate cost effective and time constrained design and
development cycles in the face of a dizzying array of implementation
options and technology choices. Increasingly, design and development
efforts are distributed both geographically and organizationally, but
must be highly coordinated at the earliest possible opportunity to
minimize false starts and ensure rapid convergence towards working
solutions which satisfy all customer requirements.
Do these challenges sound familiar I have a demonstrated track record
for delivering timely, high quality results in a challenging, dynamic
business climate. Please take the opportunity to review my background
and experience in these areas to see where I can make the greatest
contribution to the success of your organization.
In closing, thank you for taking the time to consider our mutual
interests and for exploring the ways in which we may be able to work
together in the future.
Sincerely,
John Nieznanski
OBJECTIVE:
Energetic self-starter seeks opportunity to apply extensive technical
and project leadership experience with advanced electronic design,
test, packaging and CAE technology towards applications in computing,
signal, data, or image processing, data storage / retrieval or
communications.
EXPERTISE:
PWB-MCM DESIGN / TEST / PACKAGING STRATEGIES AND TECHNOLOGIES, COST /
PERFORMANCE TRADEOFFS, SIGNAL INTEGRITY ANALYSIS, MICROVIA PWB / MCM
PROCESS DEVELOPMENT, CAE TOOL DEVELOPMENT, DEVICE MODELING, SIMULATION
(DIGITAL, TIMING, ANALOG, FAULT), PROJECT LEADERSHIP, VENDOR
EVALUATIONS, TECHNICAL PROPOSAL WRITING. ADEPT AT OVERCOMING
ORGANIZATIONAL AND FUNCTIONAL BOUNDARIES TO OBTAIN OBJECTIVES.
EXPERIENCE:
1/97
to dateELECTRONIC PACKAGING TECHNOLOGIST / ENGINEER EastmanKodak Co
., Rochester, NY
Provide technical direction and project leadership in advanced
electronic packaging technologies (microvia PWB, MCM) and signal
integrity analysis for multiple R&D and product development programs.
Focus areas include high speed digital design, high density microvia
PWB substrates, conceptual design tradeoff analysis, and noise
reduction. Research and recommend cost saving opportunities for low
cost, high volume consumer imaging products and high value, low-mid
volume office imaging, health imaging and copier products.
2/93
-12/96ELECTRONIC PACKAGING (MCM-PWB) TECHNOLOGIST / ENGINEERLockheed Sanders, Nashua, NH
Provided technical direction and project leadership in advanced
electronic packaging technologies and signal integrity analysis across
multiple Lockheed Martin programs and companies. Defined and lead IR&D
efforts. Performed technology tradeoffs, program planning support and
vendor evaluations to various programs within Sanders and Lockheed
Martin including F-22, ATIRCM and THAAD to meet cost and schedule
objectives. Headed proposal effort in response to ARPA BAA95-26 and
named program manager. Key contributor / lead author on numerous
successful proposals including Advanced Technology Support Program
(Air Force), Digital Receivers (ARPA), Digital Micro-Architectures
(ARPA). Achieved first pass success with no rework on FPGA-based MCM
built with digital HDI process. Performed signal integrity analysis of
THAAD PCBs and MCMs using QUAD tools and Mentor MCM Station. Developed
signal integrity models from vendor supplied IBIS data and HSPICE
simulations. Integrated advanced PCB and MCM CAE tools into
company-wide design environment. Knowledgeable in Known Good Die
methods. Knowledgeable in advanced MCM micro-assembly technologies
(HDI, flip chip, TAB) and advanced PWB fabrication and assembly
technologies (microvia, BGA, CSP, discrete wire).
5/92
-1/93MIXED SIGNAL ASIC DESIGN ENGINEER Aritech Corp., Hickory, NC
Initiated an IC design program to support the development of mixed
signal ASICs for use in commercial / residential intrusion and
security systems. Identified, procured and installed design
environment to support program including hardware platforms, CAD/CAE
tools and silicon foundry services. Duties included product
definition, design, simulation, physical layout, verification,
characterization and test development.
11/86
-4/92DESIGN / TEST ENGINEER GECON Consultant to GE-CRD,
Schenectady, NY
Responsible for providing technical leadership in design and testing
of MCM's fabricated with HDI process. IC technologies used include
TTL, bulk CMOS, CMOS / SOI, GaAs. Project leader / customer interface
on several programs for Air Force. Lead effort to develop die
pretest/recovery process to enable insertion of fully characterized,
burned-in, known good die into an MCM. Co-authored paper detailing
enhancements to above process for application in wafer level
processing. Developed methods for incorporating floating gate devices
which are UV erasable in die form. Developed 3-D stack technology for
RISC MCM architectures. Performed wide variety of design and test
tasks to support development of custom and semi-custom mixed-signal
ASIC's for use in high performance power supplies, ultrasound medical
imaging systems and lighting systems utilizing CMOS and BiCMOS
processes. Specific responsibilities included circuit design, device
modeling, device characterization, SPICE simulation, logic simulation,
layout parasitic extraction, design rule checking, performance testing
on both analog, digital and mixed signal subcircuits.
2/83
-10/86DIGITAL DESIGN / TEST ENGINEER Raytheon MSD, Bedford, MA
Supervised or directly performed a wide variety of logic design,
tool/library development and test development activities in support of
both CMOS VLSI gate array and standard electronic module (PWB)
hardware realization for ground-based and airborne missile systems.
Supervised the design and testing of a multifunction CMOS VLSI gate
array designed to upgrade the system performance of ground based
missile hardware through replacement of TTL devices. Designed
two-thirds of a CMOS VLSI Digital Signal Processor including all
microprogramming hardware and software as well as built-in self-test
hardware and software. Solely responsible for the concept development,
design and implementation of a Built-In Self-Test macrocell and a
design for test methodology to support both ASIC and PWB debug and
diagnostics. This testability macrocell incorporated a pseudo-random
number generator as a test vector source, a signature analyzer for
data compression, and a 4-pin off-chip I/O interface. Developed
digital cell libraries for logic simulation using behavioral and gate
level modeling. Developed and automated routines for translating logic
simulator output for usage as test vector stimuli on automated test
equipment. Designed and developed test programs and tester interface
hardware for new and existing digital circuit boards. Debugged and
fault isolated defective digital circuit boards.
EDUCATION:
B.A
. (Physics) Colgate University, Hamilton, NY
B.E
. (Electrical Engineering) Dartmouth College, Hanover, NH Thayer
School of Engineering) Thesis - "A Microprocessor Based Sidereal Clock
/ Calculator"
PUBLICATIONS / AWARDS:
MCMC-92, Santa Cruz, CA, pp. 32-35
Test cost savings idea implemented by Raytheon MSD (5/85); awarded
$5490 (10% of first year savings)
COMPUTER SKILLS:
Hardware: SUN Sparc, DEC VAX, IBM PC, Hewlett Packard O/S: UNIX, VMS,
MS-DOS, WIndows 3.1/95/NT Languages: C, Fortran, Basic, Tools:
Schematic capture, physical layout, LVS, logic simulation, analog
simulation, fault simulation, timing analysis, signal integrity
analysis, automatic test pattern generation, design rule checking,
test translators, in-circuit emulation, conceptual design tradeoff
analysis. Vendors: Mentor Graphics, QUAD, Chronology, Meta-Software,
Savantage, more
ATE / LAB EQUIPMENT:
ATE: IMS XL/2, Tektronix LT-1000, Fairchild SENTRY series
LAB:
Logic
analyzers, TDR, curve tracers, impedance / gain-phase analyzers,
oscilloscopes, waveform generators, temperature controllers,
microprobing equipment, IEEE-488 (GPIB) equipment.
PERSONAL / MISC:
Hobbies include team sports. Technical advisor to local school
districts. DoD Secret Clearance. Excellent Health.
--
John
Nieznanski Eastman Kodak
Co. mailto:abp58d@r.postjobfree.com 2/4/EP MC35313
phone: 716-***-**** 901
Elmgrove Rd. fax: 716-***-**** Rochester, NY
14653-5313 http://www.kodak.com "Take pictures. Further."
Contact this candidate