Design Power

Sumit Ahuja

*** **** **** ****, #*****, Blacksburg, VA cell: +1-540-***-**** Email:******@**.***

OBJECTIVE Seeking a job in a challenging research and development environment with an

opportunity to develop hardware, tools, methodologies for semiconductor chips.

SUMMARY OF QUALIFICATIONS

Three years of industry experience in low power hardware design and methodology development

Development of RTL power reduction methodology utilizing techniques such as clock -gating,

sequential clock-gating, power-gating, multiple voltage domains, etc.

Architected power reduction features for C2R high-level synthesis (HLS) tool

Developed RTL blocks from the algorithmic C description using HLS for IPs such as md5, AES

INDUSTRY EXPERIENCE

Member Technical Staff, Sequence Design, Noida, India Sept 2004-July 2006

Established RTL power estimation flow using PowerTheater, and power reduction methodologies by

applying techniques such as clock-gating, power-gating and multiple voltage domains for Int el,

Freescale, Samsung etc.

EDUCATION

Virginia Polytechnic Institute and State University Blacksburg, VA, USA

PhD in Electrical and Computer Engineering Aug 2006-Mar 2010 (Expected)

GPA 4.0/4.0; GRA; Published more than 12 papers in International conferences and journals

Dissertation Title: Power Estimation and Reduction Techniques for High Level Synthesis

Frameworks

Advance Learning and Research Institute, USI Lugano, Switzerland

Master of Engineering in Embedded System Design Aug 2003-July 2004

GPA 4.63/5.00; Fellowship and project sponsored by ST Microelectronics, Milan

Institute of Technology, BHU (IT-BHU) Varanasi, India

Bachelor of Technology, Electrical Engineering July 1999-May 2003

GPA 8.72/10.00 (honors); Published 3 research papers in International conferences and journals

INTERNSHIPS

Research Engineer Cebatech Inc., NJ May 2009-Aug 2009

Architected and benchmarked sequential clock-gating and investigated a new technique to enable

clock-gating based power reduction using system-level power estimation

Research Engineer Cebatech Inc., NJ May 2008-Aug 2008

Architected and benchmarked a feature for C2R HLS tool, where clock -gating can be enabled from

the C code

Graduate Technical Intern, Intel Corporation, Folsom, CA May 2007-Aug 2007

Developed a methodology for accurate and efficient power estimation from the high-level verification

collaterals that include assertions, testbenches, etc.

Summer Intern, ST Microelectronics and UBO France May-July{02, 03}

Implemented image processing algorithms using the Madeo compiler developed by UBO for

architectural analysis

SKILLS

Programming skills C, JAVA, TCL

HDLs Verilog, VHDL, SystemC, GEZEL, ESTEREL

EDA tools Power Theater, Synopsys Design Compiler, Xilinx Platform studio (XPS), VCS, Esterel

Studio, C2R, Cadence SMV

SELECTED PUBLICATIONS

More than 15 publications in various international conferences/journals

S. Ahuja, W. Zhang, S. K. Shukla, A Methodology for Power-Aware High-Level Synthesis of Co -

processors from Software Algorithms, to appear in the proceedings of International Conference on

VLSI Design, Jan 2010.

S. Ahuja, S. K. Shukla, MCBCG: Model Checking Based Sequential Clock -Gating, to appear in the

proceedings of High Level Design Validation and Test, Nov 2009.

S. Ahuja, D. A. Mathaikutty, A. Lakshminarayana, S .K. Shukla, Statistical Regression Based

Power Models for Co -processors for Faster and Accurate Power Estimation, IEEE International

SOC Conference, Sep 9-11, 2009.

S. Ahuja, S. T. Gurumani, C. Spackman, S. K. Shukla, "Hardware Coprocessor Synthesis from an

ANSI C Specification ", IEEE Design and Test of Computers, July/Aug. 2009.

S. Ahuja, D. A. Mathaikutty, G. Singh, J. Stetzer, S. K. Shukla, and A. Dingankar, "Power

Estimation Methodology for a High-Level Synthesis Framework", International Symposium on

Quality Electronic Design, Mar 16-18, 2009.

S. Ahuja, D. A. Mathaikutty, S. K. Shukla, "Applying Verification Collaterals for Accurate Power

Estimation", International Workshop on Microprocessor Test and Verification, Dec, 2008.

G. Singh, J. B. Schwartz, S. Ahuja and S. K. Shukla, Techniques for Power-aware Hardware

Synthesis from Concurrent Action Oriented Specifications, Journal of Low Power Electronics

(JOLPE), August 2007.

E. Simpson, P . Yu, P. Schaumont, S. Ahuja, S. K. Shukla, VT Matrix Multiply Design for MEMO-

CODE '07, MEMOCODE 2007.

AWARDS AND HONORS

Cebatech Inc. funded researcher for academic year 2008-09

Received Second prize at MEMOCODE 07 design contest held at Nice, France for implementing

matrix multiplication on FPGA board

Received Team Player & Excellent customer orientation award at Sequence Design, 2006

Received Best paper award for the Paper FPGA based protective r elays in All India

student paper contest organized by IEE, 2001

Among top 1% of more than 0.2 million students who appeared for the joint entrance exam

(IIT-JEE) conducted for admission to IIT s

Selected and cleared the city level Mathematics Olympiad (level-1) for the year 1996

MISCELLANEOUS

Reviewed various papers for EDA and design conferences/journals such as Design

Automation Conference (DAC), Design Automation and Test in Europe ( DATE ),

International Conference on Computer Aided Design (ICCAD), International Conference on

Computer Design (ICCD), VLSI Conference India, IEEE Journal on Circuits and Systems,

IEEE Design and Test of computers, IEEE transactions on Computers, Eurasip journal on

Embedded Systems, IEEE Embedded systems letters .

Webpage: http://filebox.vt.edu/users/sahuja/sumit.html

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