Design Project

Avinash Shetty

**** ******* ******, *** *******, CA 90007 Cell Phone : 323-***-****

Email:- abp4k1@r.postjobfree.com, abp4k1@r.postjobfree.com Website:-http://www.avinashshetty.com

OBJECTIVE

Aspiring for a challenging career that would complement my educational, technical and organizational skills.

ACADEMIC INFORMATION

Masters in Electrical Engineering, University of Southern California Spring 2005 (GPA: - 3.46).

Post Graduate Diploma in VLSI Design at CG-CoreEl Programmable Solutions Pvt. Ltd., Spring 2003.

Bachelor in Electronics Engineering, Mumbai University, 2002 (First Class, 64%).

WORK EXPERIENCE

Digital Design and Layout Engineer at Tanner Research (1 February 05 to Present).

Graduate Research Assistant at Information Science Institute (ISI/USC) (May 03 to May 05).

Trainee at Sandeepani, training division of CG-CoreEl (6 February 03 to 6 May 03).

Research Assistant at Tata Institute of Fundamental Research (TIFR Mumbai) (June 01 to May 02).

Part time Management trainee at Rachna Agrochem Pvt. Ltd. (5 January 00 to 31 May 01).

COURSES TAKEN IN USC

Mixed Signal VLSI Design, CMOS VLSI Design, VLSI System Design I, Solid State Processing and IC Laboratory,

VLSI System Design II, Computer Aided Design of Digital Systems I, Introduction to Systems Design using

Microprocessors, Technical Seminar on VLSI Design, Diagnosis and Design of Reliable Digital Computers,

Programming System Design, Logic Design and Switching Theory.

TECHNICAL ACTIVITIES

General: C, C++ and Pascal (languages); Windows98/2k/ME/XP, Mac, UNIX, Linux (platforms); HTML, Photoshop,

Flash, Dreamweaver (web). Softwares: Mathlab

Hardware languages: Verilog (Case study: Alarm Clock), VHDL (Case Study: FIFO)

Fpga Design Methodology: Introduction to Programmable Logic, Xilinx FPGA Families, Design Methodology,

Design entry, Verification, Synthesis, Configuration modes. Design Implementation.

Digital ASIC Backend: MOS Transistor theory, Mathematical modeling of Digital CMOS Inverter-Delay modeling,

estimation of power. Basic Combinational Circuits, Pass Transistor Logic & Transmission gates, Dynamic logic

circuits, Physical design/layout.

Fabrication: Wafer processing procedure including testing of fabricated devices in a class-100 clean room.

Project Management: Design Specifications, RTL Design & Documentation, Test bench Design and Documentation,

Coding and Verification, Synthesis Report, P & R Report.

EDA TOOLS

Front End Tools : HDL Designer Series, ModelSim Simulation Tool, Veriwell, Leonardo Spectrum Synthesis Tool,

Formal Pro, SST Velocity, Cadence,Altera s Quartus II .

Digital ASIC Back End Tool: Magic, IC Station, Calibre, Xcalibre, Design Architect IC, Powerview, EPD.

Analog Design Simulation : Eldo, Advance MS, Hspice, Irsim

Design For Testability: DFT Advisor, Fast Scan, Flex Test, MBIST Architect, BSD Architect.

TannerEDA:- L-Edit, Hiper Verify, Tspice .

Xilinx ISE 5: Project Navigator 5.1i, 6.1i

CURRICULAR PROJECTS

Currently involved in the Layout, LVS and DRC of BION Chip2 using XFAB XC035 Technology at Tanner

Research.

Successfully completed the Layout, LVS and DRC of APRI CLSCIC V1.0 Chip using XFAB XC035

Technology at Tanner Research.

Successfully completed the Layout and Verification of APRI Battery Controller (Tanner Labs) using Xfab

XC035 Technology.

Successfully completed the layout and verification of an ASIC for an implantable medical device (Tanner

Research).

Built a Robotic Controller for Webots Project (Tanner Labs) using C / C++ .

Built a Block Router Macro for Tanner Tools to automatically route any metal wire of any width between two

Analog or Digital Blocks specified in the input .txt file.

Web Designer and Developer for www.clearsync.com

Designer and Draftsman for Tanner Research's new office building construction in Monorvia California.

Involved in the development of ClearSync PALM project at Tanner Research.

Analyzing the requirements and limitations of switched capacitor filters in order to design an optimal approach for

the NASA chip (Tanner Research).

Built a 16 bit Microprocessor as a part of the VICAT Group at ISI using Verilog HDL. Downloaded and tested

the design in an FPGA. Funded by DARPA and BMES ERC, the goal of VICAT (VLSI Implementation of CA3)

is to develop an FPGA/VLSI device that models the nonlinear dynamics of CA3 sub region of the hippocampus.

Built and tested a Design for Test tool using C++ (EE658) and a Compiler for FPGA Based Emulation System

(EE680).

Designed and verified the 3-stage pipelined 32-bit single-precision Troy Floating-Point Unit using a RTL style of

Verilog (EE 577a).

Successfully completed the layout and HSpice simulation of 32 Bit Adder/Subtractor Using Magic.

Designed an E3 Transmitter Framer along with clock generator (34.368 MHz), Data Generator for feeding data(4

bit LFSR counter used).The coding was done using VHDL and the simulation, synthesis and implementation using

Xilinx Project Navigator (5.1i).

Designed standard cells and implemented a Full Adder using those in ICStation & Eldo.

Designed Bit Serial Implementation of an FIR Filter Semi Custom ASIC using TSMC Standard Cells.

Successfully implemented a Cryptographic algorithm, Data Encryption Standard (DES) using Ptolemy, DSP

Motorola chip56307 and Verilog as part of undergraduate research project. The project was done at the Tata

Institute of Fundamental Research, India, at the School of Technology and Computer Science, under the

supervision of Prof. R.K. Shyamasunder (Dean STCS).

Attended a workshop on "Designing with NIOS Processor at Altera's Training Institute in San Jose California.

Attended a 3 Day Workshop on VLSI Design using Verilog Hardware Description Language from 27/9/2001 to

29/9/2001 at Electronics Corporation of India Ltd. (ECIL).

EXTRACURRICULAR ACTIVITIES/ ACHIEVMENTS

Member of IEEE, IEEE Computer Society, IEEE Robotics And Automation Society, Indian Society Of

Electrical and Electronics Engineers Students Council Committee.

Member of team Stingrays (Division II) at Newport Beach Soccer League.

Was a member of Cricket and Soccer team in school, junior college and Engineering College. Captained School

for 4 years and Engineering College for 2 years.

Was a member of Team "Rallis" (Senior Division) registered under Western India Football Association (WIFA)

and Bombay District Football Association (BDFA) (Year 2000 to 2002).

Was a member of Team "Deablers" (Division II) registered under Western India Football Association (WIFA)

and Bombay District Football Association (BDFA) (Year 1996 to 2000).

Was one of the organizers of the intra-collegiate festival IEEE TECHNOFEST 2000 organized by IEEE-

Brainwaves.

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