Design Software
Resume:
Yunjian W. Jiang
*** ****** ***. ***#*** *** Cory Hall, Dept. of EECS
Albany CA 94706 University of California
510-***-**** Berkeley CA 94720-1772
http://www-cad.eecs.berkeley.edu/ wjiang ******@****.********.***
OBJECTIVE
Research and development position in the area of electronic design automation.
EDUCATION
Ph. D. University of California, Berkeley expected Aug 2003
Advisor: Robert K. Brayton
Thesis: On E cient Software Realization of Sequential Machines
Developed a design ow from synchronous speci cations to hardware/software implementation for em-
bedded systems. Built e cient algorithms for logic optimization and code generation.
M. Sci. University of California, Berkeley May 2000
Thesis: Multi-Valued Logic Network Minimization and its Applications
B. Eng. Tsinghua University, Beijing Jun. 1998
Thesis: Java-based analog circuit optimizer using genetic algorithms
Best Thesis Award in the Institute of Microelectronics, 1998.
INDUSTRY EXPERIENCE
IBM T. J. Watson Research Center, Yorktown, NY Jul. 2002 Oct. 2002
Graduate Intern Researched system-on-chip power analysis methods using state machine modeling;
developed software for dynamic power behavior analysis by symbolic simulation.
Teja Technologies, Inc., San Jose, CA May 2001 Aug. 2001
May eld Fellow Among 8 Fellows selected from Berkeley graduate students and MBA s for a program
that promotes high-tech entrepreneurship, organized by the May eld Fund. Studied both technical and
marketing aspects of the startup company s critical partnership strategies.
Cadence Berkeley Labs, Cadence Design Systems, Inc., Berkeley, CA May 2000 Aug. 2000
Graduate Intern Researched software synthesis design ows from synchronous programming lan-
guages; designed and implemented logic optimization algorithms for extended nite state machines.
Magma Design Automation, Inc., Cupertino, CA May 1999 Jul. 1999
Graduate Intern Designed and implemented timing optimization algorithms that deals with large
hardware systems.
ACADEMIC EXPERIENCE
University of California, Berkeley Spring 2000, Spring 2002
Graduate Student Instructor Assisted graduate course EECS219B on logic synthesis and veri cation
given by Dr. Andreas Kuehlmann in Spring 2002, and by Prof. Robert Brayton in Spring 2000. Gave
discussion lectures; designed homework and midterms. Mentored over 10 class projects, which led to 5
workshop and symposium publications.
Yunjian W. Jiang 2
Research Projects
MVSIS Multi-valued logic synthesis system for non-deterministic sequential networks, primary con-
tributor. Designed and implemented its Boolean optimization and code generation algorithms, and part
of its basic data structures. Software version 2.0 released in Jun. 2003.
NEXSIS Next generation synthesis for systems-on-chip. Studied area routing methodologies using
Boolean satis ability checking, and chip-level placement algorithms.
BACPAC Berkeley Advanced Chip Performance Calculator, a web-based system-level performance
estimation tool, consisting of a large set of analytical models concerning deep sub-micron e ects. Imple-
mented the core computing engine and its web interface. The software was demonstrated in a tutorial in
ICCAD 1998.
ACTIVITIES & AWARDS
Paper review for DAC 2001-2003, ICCAD 2001-2002, IWLS 2000-2002
Donald O. Pederson Electronic Systems Design Seminar co-organizer, 2001
May eld Fellows Program, Berkeley Fellow, 2001
UC Berkeley Business Plan Competition participant, 2001
IEEE student member since 1998
CalBlue soccer team member since 1998
Berkeley Chinese Entrepreneurship Forum, cofounder
Best B. E. Thesis Award in the Institute of Microelectronics, Tsinghua University, 1998
Honor Student Award, Tsinghua University, 1995-1997
SKILLS
Programming : C, C++, Java, PERL on UNIX & PC platforms
Software : GCC, Matlab, SPICE, Word, Power Point.
Communication : E ective oral presentation and technical writing skills.
REFERENCES
Dr. Andreas Kuehlmann
Adjunct Professor, UC Berkeley
Professor Robert K. Brayton Cadence Berkeley Labs
575 Cory Hall #1772 2001 Addison Street, 3rd Floor
Department of EECS Berkeley CA 94704
University of California 510-***-**** (o ce)
Berkeley CA 94720-1772 510-***-**** (fax)
510-***-**** (o ce) *****@****.********.***
510-***-**** (fax)
Professor Tiziano Villa
*******@****.********.***
University of Udine, Italy
Professor Kurt Keutzer +39-06-681*-**** (o ce)
566 Cory Hall #1772 +39-06-688*-**** (fax)
Department of EECS *****@*******.**.***.**
University of California
Dr. Reinaldo A. Bergamaschi
Berkeley CA 94720-1772
IBM T. J. Watson Research Center
510-***-**** (o ce)
1101 Kitchawan Road, Route 134
510-***-**** (fax)
Yorktown Heights, NY 10598
*******@****.********.***
914-***-**** (o ce)
*****@**.***.***
Yunjian W. Jiang 3
PUBLICATIONS
[1] Y. Jiang and R. K. Brayton, An information theoretic approach to logic evaluation, in Proc. of the Intl.
Workshop on Logic Synthesis, June 2003.
[2] R. Bergamaschi and Y. Jiang, State-based power analysis for systems-on-chip, in Proc. of the Design
Automation Conf., June 2003.
[3] Y. Jiang, S. Matic, and R. K. Brayton, Generalized cofactoring for logic function evaluation, in Proc. of
the Design Automation Conf., June 2003.
[4] Y. Jiang and R. K. Brayton, Don t cares in minimization of extended nite state machines, in Proc. of
the Asia and South Paci c Design Automation Conf., Jan. 2003.
[5] Y. Jiang and R. K. Brayton, Software synthesis from synchronous speci cations using logic simulation
techniques, in Proc. of the Design Automation Conf., June 2002.
[6] Y. Jiang and R. K. Brayton, Don t care computation in minimizing extended nite state machines with
presburger arithmetic, in Proc. of the Intl. Workshop on Logic Synthesis, Jun. 2002.
[7] M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. Sangiovanni-Vincentelli, Hw/sw parti-
tioning and code generation of embedded control applications on a recon gurable architecture platform,
in Proc. of the Intl. Symposium on Hardware/Software Co-Design, May. 2002.
[8] M. Gao, J.-H. Jiang, Y. Jiang, Y. L. A. Mishchenko, S. Singha, T. Villa, and R. K. Brayton, Optimization
of multi-valued multi-level networks, in Proc. of the Intl. Workshop on Logic Synthesis, May. 2002.
[9] Y. Jiang and R. K. Brayton, Logic optimization and code generation for embedded control applications,
in Proc. of the Intl. Symposium on Hardware/Software Co-Design, Apr. 2001.
[10] M. Gao, J.-H. Jiang, Y. Jiang, Y. Li, S. Singha, and R. K. Brayton, MVSIS, in Proc. of the Intl. Workshop
on Logic Synthesis, May. 2001.
[11] E. Dubrova, Y. Jiang, and R. K. Brayton, Minimization of multiple-valued functions in post algebra, in
Proc. of the Intl. Workshop on Logic Synthesis, Jun. 2001.
[12] J.-H. Jiang, Y. Jiang, and R. K. Brayton, An implicit method for multi-valued network encoding, in
Proc. of the Intl. Workshop on Logic Synthesis, Jun. 2001.
[13] Y. Jiang and R. K. Brayton, Don t cares and multi-valued logic network minimization, in Proc. of the
Intl. Conf. on Computer-Aided Design, Nov. 2000.
[14] Y. Jiang and R. K. Brayton, Don t cares and multi-valued logic minimization, in Proc. of the Intl.
Workshop on Logic Synthesis, May. 2000.
[15] Y. Jiang, M. Gao, S. Sinha, and R. K. Brayton, An optimizing software compiler based on multi-valued
logic optimization, in TECHCON, Semiconductor Research Corporation Technical Conference, Sep. 2000.
[16] P. Chong, Y. Jiang, S. Khatri, F. Mo, S. Sinha, and R. K. Brayton, Don t care wires in logical/physical
design, in Proc. of the Intl. Workshop on Logic Synthesis, May. 2000.
June, 2003
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