Amy McGowan

Email: aboyoo@r.postjobfree.com

Address: **** ******* **** **

City: Cumberland

State: RI

Zip: 02864

Country: USA

Phone: 401-***-****

Skill Level: Experienced

Salary Range: 95

Primary Skills/Experience:

See Resume

Educational Background:

See Resume

Job History / Details:

AMY R. MCGOWAN

3045 DIAMOND HILL ROAD, CUMBERLAND, RHODE ISLAND, 02864

401-***-**** / 401-***-****(cell) aboyoo@r.postjobfree.com

SUMMARY

Innovative PhD. Electrical Engineer with broad experience and demonstrated success in product and process research, design, development, analytical modeling, and image modeling. Skilled in reliability/quality/failure analysis engineering, quantitative modeling, statistical process control, design of experiments, project management, proof of concept, data synthesis, and bringing new products and processes on line. Regarded as a highly collaborative engineer with strong communications, mentoring, problem solving, analytical, and time management skills.

CORE TECHNICAL SKILLS

* Developing sophisticated submicron MOSFET process and device models.

* Semiconductor fabricating, IC assembly, IC test and burn-in, and discrete testing.

* Installing, characterizing, and qualifying production and test equipment.

* Verifying, characterizing, debugging, testing, and releasing new silicon.

* Analyzing failures, performing destructive physical analysis, reliability testing, FMEA and burn-in.

* Automated test equipment programming and pattern development with circuit simulators.

* Improving yields, performing failure analysis, and competitive analysis.

* Processing, digitizing, and enhancing images.

* Microscopy, Scanning Electron, FIB, Laser Emission, Infrared Emission, Thermal Emission.

EXPERIENCE

COLLABERA/QUALCOMM INC., San Diego, CA 2012 - Present

Failure Analysis Engineer II

* Perform Failure analysis for root cause analysis using advanced analysis tools on nanometer semiconductor technologies.

* Evaluate IC technologies using Megatrace CV tool, SOM Laser Emission, Infrared Emission Microscopy, Elite Thermal Emission, P-lapping, de-processing, optical microscopy, SEM, FIB, High Resolution Imaging, and Reactive Ion Etch.

* Perform physical analysis, failure analysis, and yield analysis on integrated circuits

* Investigate state of the art technologies, to assist in charting the future direction of fabrication and packaging.

RI INDUSTRIES INC., Cumberland, RI 2010 - 2012

Treasurer/Principal Product Engineer

* Define design criteria, design, characterize, implement, and test a controller for wireless trailer lights to a four prong wiring harness. Circuit board design using voltage comparators, flip-flops, and digital logic to convert turn signals into brakes, flashers and turn signals. Developed circuitry to amplify and compare the pulse input on two microphones, using test bench with scope, signal generators, etc.

* Develop customer and supplier relationships. Implement electrical board layout, software loading, and mechanical packaging.

* Design, layout and implementation of printed circuit boards, software loading and mechanical packaging. Implementing electrical board into Eagle layout for surface mount implementation.

* Define design criteria, design, debug sonic flow meter and sensing controller.

* Develop and implement accounting packages, keep corporate accounts and taxes, track and analyze corporate financial stability.

ANALOG DEVICES INC., Norwood, MA 2000 - 2010

Principal Product Engineer

* Characterized new products, analyzed data, developed, released/correlated test programs, resolved customers` issues, and minimized test time while maximizing test coverage.

* Developed and supported qualification and reliability testing of new die, packages and processes by defining material use, developing ESD and Latch-up tests on automated IC test equipment.

* Brought up new silicon, interfaced with application, design, overseas fabrication, and assembly to resolve yield issues. Worked FMEA on new products and yield crash with offshore fab, design and application engineering. Developed new startup patterns to initialize the PLL.

* Wrote, reviewed, and approved datasheets, test programs, and characterization reports.

* Developed Comparative Analysis between ADI and competitor`s products including ALU and peripheral device features, device and operating performance, benchmarks, memory, die usage, wafer and assembly technology, manufacture and test cost comparison, and yield versus cost comparisons.

* Directed reverse engineering of competitor`s die and developed web page to share information on competitor`s die usage and technology.

* Performed root-cause analysis and identified previously unexplored voltage floors, which initiated die revision to eliminate or minimize future, yield losses. Debugged test issues on new and early production ICs. Developed automated testing to step and repeat patterns looking for very intermittent customer issues.

* Partnered with production to ensure on-time customer deliveries of prototype and sample devices, negotiated tester priorities, improved test boards and standards, and evaluated product yields.

* Correlated test programs and devices with overseas wafer fabrication and test/assembly houses.

* Provided global technical support for wafer fabrication, package assembly, and electrical test.

* Successfully reduced test times tenfold, implemented dual timing routine to improve product yields, and improved yields 20% on largest volume DSP.

* Oversaw Release-to-Production, simulating, transposing, creating, and ensuring compatible pattern development.

* Trained, mentored, and coached a junior engineer and technician to support ongoing products.

UNIVERSITY OF COLORADO, Colorado Springs, CO 1996 - 2000

Research/Teaching Assistant

* While pursuing a Ph.D., I taught integrated circuit fabrication laboratory, focusing on industrial methods and lecturing on defect analysis, etch methods, chemical effects, and equipment development.

* I developed a completely analytical 2-D model for a submicron MOSFET in which the diffusion coefficient is dependent upon the doping concentration. For the first time, the analytical link between the variable doping concentration and the device characteristics had been solved. MINIMOS and Silvaco`s Virtual Wafer Fabrication simulation packages provided a comparison of standard models with analytic process sensitive device models.

MARITIME DESIGN INC., Northborough, MA 1995 - 2000

Secretary/Treasurer and Principle Engineer

* Founder and co-owner for start up firm.

* Responsible for designing test environment supporting project control software on multiple operating systems (SUN, VMS, NT).

* Responsible for managing the financial aspects of Maritime Design including all tax forms and payments, payroll, workman`s compensation, invoicing, and debt collection.

WORCESTER POLYTECHNIC INSTITUTE, Worchester, MA 1999 - 2000

Adjunct Professor

* I taught the Mechanics of Physics recitation and laboratory to freshmen through seniors, focusing on problem solving. The laboratory included focused on the implementation of vectors and forces.

COLORADO TECHNICAL UNIVERSITY, Colorado Springs, CO 1995 - 1996

Adjunct Professor

* TI taught Digital Design Courses and Laboratories to sophomore, junior, and senior students introducing advanced comparative architectures. The laboratory included PLAs, leds, and switches to solves varying difficulties in logic design.

DIGITAL EQUIPMENT CORPORATION, Hudson, MA 1988 - 1995

Senior Quality Engineer

* Characterized equipment, assessed processes and systems per ISO 9000, analyzed data, designed experiments, MRB, SPC, developed qualification requirements, resolved customers' issues, drove corrective actions, and reduced defects.

* Provided technical and quality support for the wafer fabs, package assembly, electrical test, and burn-in.

* Team designed an Automated Inspection Vision System for wirebond defects, demonstrating 95.5% accuracy and obtaining competitive corporate research funding for three engineers.

* Process Analysis Paper: "Neural Network/Machine Learning Approach to Automated Wirebond Defect Classification"

* Designed innovative qualification plan using SPC, process characterization, and incremental process release to minimize standard reliability tests.

* Taught Basic Problem Solving Techniques. I was a member of Women at Work Committee which brought in speakers promoting diversity in the workplace.

NCR - MICROELECTRONIC DIVISION, Colorado Springs, CO 1986 - 1988

Product Assurance Engineer

* Worked with customers, analyzed returns, qualified off-site testing, defined outgoing metrics, analyzed failures, and tested product reliability.

* Designed and completed Pressure Cooker versus Autoclave life testing experiment.

* Determined reliability and burn-in testing and defined screening requirements for material that failed quality-sampling tests.

* Wrote inspection and test criteria for quality sampling. Used Design of Experiments to improve wafer yields.

* Reported outgoing electrical and mechanical quality and reduced defect levels to 200 ppm.

* Developed Ship-to-Stock and Preferred Vendor presentations for automotive customers.

* I represented NCR at customer site for process change acceptance.

UNIVERSITY OF COLORADO, Colorado Springs, CO 1984 - 1986

Research Assistant Microelectronics Lab

* Designed and implemented new process techniques for ferroelectric ICs. Investigated thin film ferroelectric deposition on silicon wafers. Established a comprehensive ferroelectric library.

* Team established the first MOS line at UCCS: Specifically: rebuilt furnaces, vacuum systems, and gas panels. Characterized ion implantation, chemical deposition and etch, wet etch and clean processes, plasma deposition, and metal deposition processes.

* Instrumental in layout, purchasing, and installation of analysis laboratory.

* Processed first MOS transistors at UCCS from bare silicon to device characterization.

* Analyzed ICs using SEM, EDS(x-Ray Dispersion Analysis), IV and CV testing.

TRW/ELECTRONIC PRODUCTS INC., Colorado Springs, CO 1980 - 1984

IC Test Programmer, Senior Material Controller, and Destructive Physical Analysis Technician

* I received three promotions in three years due to extraordinary performance.

* Performed destructive physical analysis (DPA) of integrated circuits, thin film, tantalum slug and ceramic capacitors, resistors, inductors, and other discreet components for military and space systems. Used Xray, disection, diamond saws, polishing wheels, photographic documetation, and wire pulling techniques.

* Developed new DPA testing procedures and computer tracking systems.

* I scheduled inspectors work loads in receiving inspection.

* Designed programs for automated test equipment. Interfaced HP85 with existing test equipment.

* I taught in-plant course on programming.

SECURITY CLEARANCE

Department of Defense Secret Security Clearance at TRW

COMPUTER SKILLS

* Languages: Basic, Fortran, DCL, Perl, Cshell, C/C++.

* Systems: Solaris 5.8, Windows 7, Windows XP, Windows NT, VMS, MS DOS, Windows 3.1, and Windows 95/98, Teradyne j971, Teradyne j973, Verigy 93K, linux Redhat.

* Software Packages: Camelot, Yeild Explorer, Mathcad, Silvaco: Virtual Wafer Fabrication, Harvard Graphics, RS1/Discover/Explore, COMETS, SAS, XV, misc. editors and spreadsheets, Office 2007, datatool, Megacrunch, crunch etc.

EDUCATION

Ph.D., EE Solid State Physics, UNIVERSITY OF COLORADO, Colorado Springs, CO

Dissertation: -A Process Sensitive Device Model for Submicron MOSFETs-

Master of Science, EE Solid State Physics, UNIVERSITY OF COLORADO, Colorado Springs, CO

Thesis: "Characterization and Design Considerations of a Metal Ferroelectric Oxide Field Effect Transistor"

Bachelor of Arts, Biology, CASE WESTERN RESERVE UNIVERSITY, Cleveland, OH

Research: "Euthyroid Sick Syndrome in Psychiatric Patients"

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