Project School
Resume:
Page *
CENTRE FOR DEVELOPMENT OF ADVANCED COMPUTING,
KOLKATA
ICMARD Building (7
th
Floor), CIT Scheme VIII(M)
Ultadanga, Kolkata 700067
Phone :033-****-****/29,033-****-**** Fax:033-****-****
DIPLOMA IN VLSI DESIGN DVLSI - AUGUST - 2005 BATCH
RESUME
ANDE KRISHNA DURGA PRABHAKAR
Tel No. : 024**-******
E-mail: andhe1983@*****.***********@**********.***
PERSONAL DETAILS
Gender
:
Male
Marital Status : Unmarried
Date of Birth : 12
th
January 1983
Hobbies : Reading, Playing Carroms, Surfing etc.
Languages
: English, Hindi, Marathi, Telugu.
Known
Page 2
EDUCATIONAL QUALIFICATION :
Awards/Achievements
: 1. GATE 2005 94.33%
SOFTWARE : C, LINUX.
HARDWARE SKILLS : Assembly Language- 8085,8086.
VHDL,VERILOG,
Xillinx ISE 6.1i
including XST synthesis tool. Implemented designs on SPARTAN,VIRTEX Kits
Experience (if any):
S.No
Organisation
No. of
years
Designation
Nature of work
Qualification Branch / Stream
Year of
passing
College/School
University/ Board
Percentage
of Marks
PG
DIPLOMA
IN VLSI
2006
CDAC,Kolkata
B.E.
ELECTRONICS 2004
M.S.Bidve college
of engineering,
Latur.
Swami Ramanand
Teerth
Marathwada
University,
Nanded.
Maharashtra.
70.51
H.S.C [12
th
class]
Mathematics
[Group:MPC]
2000
Dayanand Science
College,Latur.
Board Of
Secondary and
Higher Secondary
Education,Pune.
Maharashtra.
[Latur Divisional
Board]
79.00
S.S.C[10
th
class]
1998
Kripa Sadan
Convent High
School,Latur.
Board Of
Secondary and
Higher Secondary
education,
Pune.Maharashtra
[Latur Divisional
Board]
73.46
Page 3
Projects Description:-
I)
B.Tech Project : Data Acquisition Using VHDL.
In this project we implemented UART on FPGA and have displayed the measured temperature
Over Hyper terminal on the PC. For this purpose we have used Xilinx CPLD as the target
device.
The HDL used was VHDL.
II) DVLSI Project : Yet to be finalized.
ANDE PRABHAKAR
[NAME
Contact this candidate