Design Project

Guan Wang

University of Florida Email Address: **************@*****.***

Master of Science Phone Number: 352-***-****

Electrical and Computer Engineering Address: 555 Umbarger Road Spc 80, San Jose CA 95111

Objective

* To obtain a full time position for Digital Circuit Design, Verification and Test Engineer

Education Background

University of Florida GPA: 3.76/4.0 MSEE Graduated: May 2012

Excellent marks in VLSI Circuit and Technology (A), Reconfigurable Computing (VHDL/FPGA) and Bipolar/MOS Analog IC Design (A/A-) courses, Microwave, RFIC Design, RF Circuits and Systems and Fundamentals of Data Converters

Xi’an Jiaotong University (Xi’an, China) Score 87/100 B.S. Electronics Graduated: July 2010

Major Courses: Semiconductor Physics, Dielectric Physics, Solid State Physics, Signal Integrity and Systems, Analog Electronics, Digital Logic Circuit Design, Digital Image Processing, Microcomputer Principles and Interface Techniques

Academic Research Experience

5-Stage Pipelined MIPS Processor Design Project University of Florida, April 2011

Experienced in designing pipeline architectures from behavioral design to layout implementation and characterization.

The final Advanced VLSI design project consisted of a team of five for an 8-bit MIPS processor with low power stacked SRAM design. Tasks involved were architecture design, VHDL coding, power minimization and memory design.

My part was to design the controller and the 10-T sleepy SRAM custom layout.

SRAM Circuit Design Project University of Florida, December 2010

The final VLSI Circuits and Technology project consisted of a team of 2 people for an 8-bit SRAM design.

The task concludes 6T SRAM schematic and layout design. Work done: SRAM Layout

Time-Domain Convolution Design Project University of Florida, December 2011

On top of the Pipeline Architecture the project comprised of Glue logic, Controller, Smart buffer, Datapath and SRAM design. (Clock domain: FIFO & Handshake & Dual Flip Flop). Individual work consisted of VHDL/C coding.

Created a custom circuit implemented on the Nallatech board that exploits a significant amount of parallelism.

Fibonacci Calculator University of Florida, September 2011

Implement a circuit in VHDL that calculates Fibonacci numbers. First part is the controller and datapath design while the second part is implementation of the circuit on the Nallatech board and connected to an FPGA to get the output.

A Fully Differential 12-bit Pipeline ADC University of Florida, December 2011

Transistor level op amps, comparators and switches. Work concentrated on comparators and all digital parts.

Accurate first MDAC, high op amp’s gain and capacitance scaling was required. Linearity and settling time were characterized.

A 2.4 GHz Two-Step CMOS Receiver Transistor level Receiver University of Florida, December 2011

Transistor level LNA (2.4G), Mixer (2.4G/0.8G), Divide by 2 Circuit, BPF (0.8G) was done.

My work focused on the Mixer & BPF.

Technical Skills

Experienced in Cadence Virtuoso Schematic, Layout and Simulation, LTSpice software and VHDL coding

Knowledgeable in RTL Design, Verilog, C++, Assembly Languages, Unix/Linux shell, Perl, Python and Matlab

Proficient in Agilent ADS, Design Compiler, IC Compiler, Xilinx ISE, AutoCAD, Network Analyzer, Digital Oscilloscope

Industrial Experience

Internship: Dalian Sievert Testing Equipment, China; full-time; Testing communication system using GSM; June to July, 2011

Internship: Beijing Optoquantum Company, China; part-time; Studying electronic circuits and devices; August 2009

Honors

2008 National Encouragement Scholarship, China

2010 Achievement Award Scholarship, University of Florida

2011 Certificate of Outstanding Achievement, University of Florida

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