Electrical Engineering

Tong Zhang

Email: *********@********.***

Address: ***** ********* **

City: Cupertino

State: CA

Zip: 95015

Country: USA

Phone: 646-***-****

Skill Level: Assistant

Salary Range: 70

Willing to Relocate

Primary Skills/Experience:

See Resume

Educational Background:

See Resume

Job History / Details:

TONG ZHANG

10281 Vicksburg Dr. Cupertino, CA 95014 646-***-**** *********@********.***

EDUCATION

Columbia University, Fu Foundation School of Engineering and Applied Science New York, NY

MS in Electrical Engineering Expected December 2012

Coursework: Digital VLSI Circuits, Advanced Logic Design, Computer Architecture, CAD of Digital Systems, Embedded Systems, Advanced Digital Electronics Circuits, Formal SW & HW Verification, Computer Hardware Design

Harbin Institute of Technology, School of Electronics and Information Technology Harbin, China

BS in Communication Engineering (Microwave Technology) July 2011

INTERN EXPERIENCE

ALTOBEAM Beijing, China

ASIC Design Engineer Summer 2012

ai Participated in the Merlin project designing high-performance receiver for digital television.

ai Designed RTL modules in Verilog HDL to develop algorithms in Matlab, and verified them by writing testbenches in Verilog and Matlab and did large numbers of tests randomly by script files wrote in Perl and Makefile

ai Set up the FPGA test environment, including collecting all related design modules and check for syntax errors, PIN assignment, writing sdc (Synopsys Design Constraints) file, running the simulations and synthesis, and report the timing and LUT utilization results.

PROJECT EXPERIENCE

Columbia University New York, NY

Design of a Low Power Digital Signal Processor Spring 2012

ai Designed a 32-bit microprocessor for DFT, IDFT and convolution operations, applying several low-power technologies, such as clock gating and multiple supply voltages, to minimize its power. The designed processor is capable of dealing with different data lengths (2n, n varies from 1 to 16), and has specially designed hardware part for SRAM address calculation

ai Implemented the design in System Verilog and wrote testbenches to verify its performance

Design of a Small CAD Tool for Logic Miniaturization Spring 2012

ai Designed a CAD tool in C based on unate recursive paradigm for generation of prime implicants from the input set of covers and identification of the essential ones. Functions built in the tool include: Termination Rule Checking, Tautology Checking, Consensus Generation, Single-Cube Containment, and Split variable picking

ai Verified the tool with designed input PLA files covering all different kinds of initial covers

Design of a Small Microcontroller Core Fall 2011

ai Designed a 8-bit microcontroller core consisting of ripple carry adder, barrel shifter, MUX, SRAM, latches, bus driver, buffers and a pseudo NMOS PLA for 6-bit instruction word in IBM 90nm Technology

ai Realized the design in schematic and layout with Cadence and verified its function with Spectre and Ultrasim simulations

RTL Design of a Hybrid Floating-Point Integer Adder Fall 2011

ai Detailed design of a special adder with an integer and a floating number as operands, including its Pseudo code, Algorithmic State Machine (ASM), architecture and microarchitecture, state diagram and Finite State Machine (FSM)

ai Implemented the design in VHDL and write testbenches to verify its performances with Quartus tool

Optimization of the Longest Common Subsequence (LCS) Microprocessor Fall 2011

ai Applied a more efficient algorithm and rewrote the software part in C

ai Adjusted the hardware configurations of the processor, such as core type, memory hierarchy, cache configuration and clock frequency, to minimize the execution time within the cost and RAM size limitations

SKILLS

ai Applications: Origin, Excel, MS Word, PowerPoint, MS Visio, Endnote

ai Research & Development: Matlab, Quartus, Cadence, Advanced Design System, CST Microwave Studio(R)

ai Programming Languages: C, C++, Verilog HDL, System Verilog, VHDL, Perl, Tcl

ai Language Skills: Fluent in Mandarin

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