Engineer Design

Gaurav Sharma

* ******** *****, ********, **,L*R 1L9

Email: aboqma@r.postjobfree.com

Contact: 647-***-****

CAREER OBJECTIVE

To be a part of an ambitious & professional team, working on challenging missions and critical tasks, which offer potential growth and development through dedicated individual as well as team effort. Create a niche in cutting edge technologies through career growth.

PROFILE

Self motivated, organized, team player and quick learner design/application engineer (M. Tech. Microelectronics) with competent knowledge and more than ten years of experience in back end full and semi custom layout design and circuit simulation of digital, mixed analog and RF circuits in various CMOS and Bipolar technology generations (0.25um to 28nm) with floor planing, physical verification and RC extraction. Having background of ultra low power FPGAs, ASICs, ADCs, DACs, SRAM & ROM Memory compiler characterization and verifications.

CAREER HIGHLIGHTS

Compact layout design of Sense amplifier, memory cell and LDO which were regarded as reference by other departments.Taped out compiler with characterization and validations with layout changes in 45 days which takes normally 60 days, hence resulted revenue in the running quarter.Shrinked the switch box layout for FPGA core by 12% which resulted in 18 % lesser power dissipation, hence fulfilled the requirements of Customer.Got the best performer award two times for resolving customer's issues efficiently.Introduced improvements in compiler flow.

SUMMARY OF TECHNICAL SKILLS

Schematic & Layout Design : Cadence OPUS, VXL, Calibre, P&R

Synopsys : Railmill, Powermill,Design Analyzer

Simulation Tools : Mentor Graphics (ELDO, Xelga),Avanti (Hercules, HSPICE) HSIM and Spectre

RC Extraction Tools : ARCADIA, STAR-XT

DRC & LVS Verification Tools : Calibre, Hercules, Assura, Diva

Operating Systems : Unix, MS-Dos, Windows

Programming Languages : C, FORTRAN,Verilog,VHDL, Unix Shell scripting

Layout technologies : 250nm, 180nm, 150nm, 130nm, 90nm, 65nm, 28nm

Foundries worked with : TSMC, CSM, Infineon, IHP, IBM, Intel

CORPORATE EXERIENCE

July 2011 to April 2012 : Intel (Semiconductor) (Germany)

Successes at this position as a consultant: 28nm technology in RF circuit layout designLayout design (leaf cell to top level with floor planning and physical verification) of RF and mixed analog mobile test chip in 28nm LP technology. Designed the layouts of major blocks (LDOs, BandGap, Biasing circuits) for Synthesizer, Transmitter & ( Biasing blocks, clock trees,clock divider) for Receiver section.Very quickly learned and delivered layouts for Tlines, utilized and suggested improvements in Qgen and guard ring tool.Integration of major blocks on the top chip level and suggested changes for the blocking

layer to separate digital and analog stuffs and provided better isolation.

Oct. 2009 to Jan. 2011: Advico Microelectronics (Semiconductor) (Germany)

Successes at this Position as ASIC/Application Engineer: Two members were reporting to meLayout design for a test chip and sorted out customer's issues for IHP foundry in 0.13um technology for the process verification with various timings.Layout of Ring Oscillators (0.13um tech.) and determination of highest operating frequency,pad frame design, redesigned ESD pad upon customer's request.Improvement introduced into layout and circuit of Band Gap Reference circuit for better curve corrections. Layouts of Opamp and PLL completed very accurately. Characterization done for Analog to digital converter and Digital to Analog Converters with Spectre test benches generation, simulations and verified some blocks in Verilog. 50 % reduction achieved in layout design for ADC 12 Bit chip(10Mb/s) from 0.25um technology into 0.13um technology and provided characterization for the full chip. Changes introduced into characterization flow of ADC ASICs.Documentation done for the customers for the templates of sub blocks and top level chip with layout simulation results for the Analog to digital converters and Test Chip.

July 2007 to June 2009: Actel (Semiconductor)(Germany)

Successes at this Position as Sr. Design Engineer:Successful layout design of IGLOO2 (130nm) at Actel without additional space after insertion of new devices in scan section, this made the customer very relaxed.Very compact Configuration block layout design for G4 series (ProAsic 65 nm) using upto metal 9 layers.Hspice IR drop analysis and simulation for core of G4 product for FPGA in 65nm technology,which was great help for determining the power line widths. Floor planning & Physical design for core of FPGA for the G4 product of ProAsic series in 65nm technology. Provided maximum number of double vias (via 1 to via 8) for the FPGA core to improve yield .Analog layout for charge pump for PLL, VCO, sense amplifier, sense multiplexer, operational amplifiers including parameterized cells and passive devices. Layout design for the device Nano and Fusion2 by Actel with appreciation from top management.

July 2006 to July 2007 Virage Logic (Semiconductor) Noida India

Successes at this Position as Sr. Application Engineer Layout design performed for the memcell, sense amplifier, IO section, control section for a dual port 90nm LP and resolved memory compiler issues reported by customer. Sorted out customer's issue of missing cell contents problem using the scrambler tool.Layout design for a 90nm GP memory compiler major blocks in 45 days with a tremendous pressure from customer, otherwise it takes 60 days at least, provided technical documentation.Simulation of memory compilers and detection of various design margin failures and analyzed them and satisfied the needs of customers.Generation of GDSII database, power files, leakage files which goes directly to customers and control of file with some special features which makes customers limited to use them. These files were generated with UNIX & shell scripts.

March 2001 to July 2006 ST Microelectronics (Semiconductor) Greater Noida India

Successes at this Position as Design Engineer: Two members were reporting to me Compact layout design for memory cell and sense amplifier in 0.13um / 90nm technology which was regarded as reference by other groups like R & D also.Designed layouts for the leaf cells for memories starting from row & column decoders, control block, Input Output Sections. Integration of blocks upto the top level of chip.Memory cell analysis & sense amplifier analysis and layout work carried out for memories.Critical path generation and simulation of memory with a very accurate modeling of loads.Power & Electron Mobility analysis with changes in power tracks. Successfully carried out tape outs with full layout work of memory projects from 130 nm to 90 nm technology.Significant saving of 10 um in x direction for switch box of FPGA tile with layout design.Clock tree analysis and layout design with proper matching of load for FPGA core.Schematic entry for the FPGA core by using design analyzer and its layout implementation.Characterization & verification of ROM compiler in 90 nm technology with layout changes.For a low power compiler 65 nm technology, Customer reported design failure at 0.95 Volt support, originally it was supported at 1.0 Volt. It was Write failure; I proposed and implemented the pull devices with a particular RM setting and without acquiring additional space.

PROFESSIONAL EDUCATION

Master of Technology (Microelectronics)

Panjab University Chandigarh (India)

Personal Interests & Hobbies

Singing,Imitating,Jogging, Yoga,Book Reading, Traveling

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