Design Engineer
Resume:
Jed Griffin
Email: *********@********.***
Address: **** ********** **
City: Peyton
State: CO
Zip: 80831
Country: USA
Phone: 719-***-****
Skill Level: Experienced
Salary Range: 100
Willing to Relocate
Primary Skills/Experience:
See Resume
Educational Background:
See Resume
Job History / Details:
Jed Griffin
*********@********.***
9275 Rockingham Drive
Peyton, CO 80831
I am looking to contribute my analog/mixed-mode design skills to augment successful IC products. My competency is analog, integrated-circuit (IC) design. Innovative achievements from my work as an analog design engineer have contributed to the successful implementation of challenging IC products by meeting design specifications not possible to meet with existing state of the art.
SALIENT INNOVATIONS
Dual-Reference Phase Locked Loop (DR PLL) and Delay Locked Loop (DR DLL)
Dual-reference phase tracking that locks a resultant phase between the 2 phases that comprise a reference clock. This removes the conflicting design goals of traditional single-reference tracking PLLs/DLLs, by allowing for very high loop gain, fast tracking bandwidth and short acquisition time, and no loop filtering required for minimizing jitter amplification and peaking associated with traditional single-phase tracking PLLs/DLLs. The frequency conveyed by 2 phases also allows a DR PFD that eliminates frequency aliasing.
a United States patent on DR DLL, US 7,936,194 (Intel patent)
a United States patent on DR PLL, US 7,629,847 and US 7,990,224 (Atmel patents)
a Paper and presentation given at DTTC 2006 Design Conference
Large-Signal Active Resistor
CMOS analog sub-circuit, similar to current sources and voltage references, an active resistor with constant resistance independent of voltage (resistance reference). Provides linear large-signal resistance to be accurately set and track to other transistors across operating conditions.
a International patent and United States patents US 6,137,317 and US 6,400,176
a Published and presented at IEEE 42nd Midwest Symposium on Circuits and Systems, aLarge-signal Active Resistor Output Drivera
Matched-Currents and Opposing-Currents Differential Amplifiers
Matched-currents with near constant phase shift and near constant differential gain across wide range of common modes. Apart from wider CMR, operation to lower voltages than traditional differential pair configuration is achievable while maintaining similar or improved performance for GB, CMRR, PSRR, and VOS. Opposing-currents have an order of magnitude higher Gain-bandwidth (GB) than achievable with differential pair configurations. Stable, closed-loop operational amplifiers with greater than 100dB amplification were realized.
a United States patent US 6,411,132 (also patents US 6,489,821 and US 6,621,313) used in Pentium 4 PLL (Intel patents)
a Patent on Opposing-currents, US 7,629,847 (Atmel patent)
a Published and presented at Intel Design and Test Technology Conference (DTTC) 2000, aMatched Current Differential Amplifiersa
a Received aOutstanding Presentationa award at DTTC 2000 Design Conference
a Presented at IEEE ISSCC (Solid-state Conference) 2003
Controlled-Frequencies, High-Speed Communication Link
A physical layer that eliminates ISI in data communication; it also alleviates other high-speed-transmission impediments.
a United States patents US 7,224,739, US 7,308,025, US 7,158,594, US 7,305,023
ACADEMIC
Bachelor of Science, Electrical Engineering, emphasis in analog CMOS circuit design (Masters Courses)
University of Colorado, 1993
Bachelor of Science, Computer Science
Utah State University, 1986
PROFESSIONAL HIGHLIGHTS
Atmel a Colorado Springs, Colorado February 2007 to present
Implemented analog circuitry for chips used in printers, hand-held devices, and embedded security applications.
a Designed a bandgap with chopping to keep device noise well below 10uVRMS from 100 to 100kHz
o Power was kept below 5uA with chopping at 150kHz
o PSRR was -80dB at DC and -70dB at 1kHz
o Accuracy kept to with 0.3% accuracy across -40 oC to 150 oC
a Designed an LDO with n-channel output
o Power was kept around 10uA with chopping at 150kHz
o Dropout was kept below 60mV
o PSRR of -80dB with optimal line and load regulation
a Evaluated charged pumps and evaluated buck-boost switched regulators for LED backlighting
a Innovated a new Dual-reference PLL used across multiple products to eliminate jitter peaking
o High synthesis ratio was achieved while maintaining very high tracking bandwidth
o PLL inherently eliminates frequency aliasing, benefiting from two reference phases
o Enabled difficult to achieve FM demodulation in RF because of fast tracking bandwidth
o High gain VCO with low phase error, with patent US 7,994,869
a Innovated a new high gain-bandwidth Opposing-currents differential amplifier
o Order of magnitude higher gain-bandwidth than optimally sized differential pair
o Enabled stable (frequency compensated), 3 stage, 100dB operational amplifiers
a Innovated a low phase noise DLL for use in high data rate I/O
a Designed Nyquist and Integrator (Delta-sigma) ADCs with high resolution
a Innovated differential capacitance sensor, used as a humidity sensor with off-die capacitors
a Designed a low-power ROM
a Innovated a new self-calibrating temperature sensor (no die-to-die adjust costs incurred)
o Sensitivity 0.7mV/ oC (ADC Sensitivity 1.19bit/ oC) from 2.5V to 5.5V with no calibration
o Silicon measured accuracy 1.26 oC over -15 oC to 100 oC range
o Silicon measured accuracy 2.1 oC over -40 oC to 100 oC range
o Simulated next generation 1 oC over -50 oC to 150 oC
a Innovated a new Binary Divarication DAC with the DNL of R2R of equivalent power and area
a Designed countermeasures for DPA attack, isolating on-die activity from power pins
a Designed a Power-on Reset (POR) detector
o POR signals other circuitry when hand-held battery has degenerated too low
o Designed a Power-on Reset (POR) detector
Intel - Hillsboro, Oregon June 1997 to February 2007
Worked in an analog design group to provide key analog circuitry to cross-site groups.
a Assisted Pentium 4 on using match-current differential amplifier in new PLL design
a Consulted other process groups on using large-signal active resistors as terminating resistor
a Assisted other product groups to implement matched-current differential amplifiers
a Developed initial concept and assisted design team in Arizona on implementing a DR DLL
a Assisted in the design of 4GTS high speed serial link
Provided key contributions to custom circuit design for server chipsets.
a Delivered I/O cells for PCI, AGP 1x to 4x, and memory buses with successful first silicon
a Innovated and developed a Dual-Reference (DR) phase tracking, implementing a DR DLL
a Designed new temperature sensor with linearity over range from 0 oC to 130 oC
a Designed, developed, and patented a broad range of custom analog circuits
o Matched-current differential amplifiers with much closer to ideal behavior
o High resolution and high sample rate AD and DA converters
o Controlled-frequencies, eliminating ISI and alleviating other high speed effects
o VCO with tight duty cycle across wide range of frequency, US 6,498,539
o Designed circuitry to generate random numbers by amplifying flicker and thermal noise
NEC America (Contractor) - Hillsboro, Oregon January 1997 to June 1997
Provided sensing circuits for monitoring environmental conditions to provide feedback used in adjusting the operation of control circuits.
a Designed temperature sensing circuits and fan monitoring circuits for a fan shelf controller
a Rigorous constraints from the harshest of conditions in nature had to be allowed for
Applied Microsystems - Redmond, Washington May 1996 to January 1997
Designed targets around Intel x86 and Motorola microprocessors.
a Used Concept for schematic capture and other Cadence tools in design verification
a Utilized Lattice and Xilinx PLDs to decode memory map and design slave devices
Microscan/Pacific ID (Contractor) - Renton, Washington January 1996 to May 1996
Designed small-signal amplifiers to stage to signal conditioning circuits and to ultimately supply a clear signal to bar code decoders.
a Biased amplifiers and photodiode in a complementary configuration to maximize linearity
a Decoded bars and spaces in Code 16k using signal processing cross-correlation
Microsoft (Contractor) - Redmond, Washington April 1995 to December 1995
Developed and coded custom UI for MS World Atlas.
a Developed features using C++ with MFC in Win95
a Developed Find and Settings features with complex elements such as slide out windows
Optronics a Salt Lake City, Utah January 1994 to March 1995
Designed circuits around CCD to detect and measure velocity and position of moving objects.
a Designed a stereoscopic optical sensor using Law of Sines
a Designed two-phase clocking and amplifier circuits around sensing CCDs
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