Engineer Electrical
Resume:
CHAITANYA KOLLURU
San Jose, CA - 95132 abobex@r.postjobfree.com
Objective Seeking a challenging position in a reputed organization where my skills and abilities are best utilized as
well as enhanced.
Education Master of Science-Electrical Engineering [Dec 2012]
University of Missouri- Kansas City GPA-3.2/4.0
Bachelor of Technology-Electronics & Communication Engineering [May 2010]
Jawaharlal Nehru Technological University GPA-3.7/4.0
Technical Skills
• EDA tools: Cadence Virtuoso, Hspice, SynaptiCAD, ModelSim, Synplify, Xilinx Place & Route, Xilinx Project
Navigator, Xilinx ISE, avr32studio.
• Hardware descriptive languages: Verilog HDL, VHDL, System Verilog(beginner)
• Assembly languages: Intel 8085/8086 and 8051 microcontroller.
• Programming Languages: C& Data Structures, C++, Java, Perl, MATLAB, OPNET.
• TCP/IP, VoIP, MPLS, Routing and Switching Protocols, LAN, VPN
• Cellular Technologies: 2G, 3G, 4G LTE, LTE-A and WiMax
• Operating Systems: Windows 2000/XP/Vista/Windows 7, and Linux.
Relevant Coursework
Analog and Mixed IC design, Logic Design, VLSI Circuits, Digital Circuits & Systems, Verilog HDL, Computer
Architecture, Embedded Systems, Wireless communications, Network Architecture, Computer Arithmetic,
RF/Microwave Engineering, Radar Systems.
Profile Summary
• Proficient and accomplished Electrical Engineer with hands on experience in Verilog, VHDL and System
Verilog(beginner), Cadence Virtuoso and MATLAB.
• Strong educational background in VLSI, ASIC design, with experience in RTL schematic and layout generations, pre
and post-layout simulations, synthesis, place and route functions.
• Expertise in handling Layout design, Layout Vs Schematic check and Post- Layout simulation.
• Learning ASIC verification out of interest in the field. Knowledgeable in developing functional coverage,
implementing verification environment, test-benches and formal verification flows.
• Hope to develop into a resourceful verification engineer in near future.
• Headed a student-run club for Electrical Engineers, organized events and activities of the club. Helped students by
providing technical assistance and supervised projects in the field of Electrical Engineering.
• Motivated individual, who loves to participate and work with people.
Experience
• Butterfly Labs, Kansas City, MO
Assistant Hardware engineer (internship) [Aug 2012-Sep 2012]
Build BITFORCE SHA256 mini-rig units housing printed control boards containing ATMEL chip, used
significantly in bit-coin mining applications and for high processing requirements.
Debug and test system performance for robustness, durability and peak capacity using avr32studio.
Devise methods to improve performance and stability of the units.
• Teleparadigm Networks Ltd., Hyderabad, India
Assistant Network Engineer (internship) [Dec 2009-May 2010]
Worked on the project ‘Implementing MPLS’
Design a MPLS system using two nodes and replicate the functioning of the system.
Build codes and design mechanisms to analyze its functioning and performance.
Downscale the architecture of MPLS to the current setting and incorporate the functioning into the
nodes.
Account for usage and efficiency of MPLS mechanism in today’s networking industry.
Academic Projects
• Analysis of discrete time Switched Capacitor Integrator
Paper and pencil analysis of its functioning and overall performance.
Analysis using Cadence Tools- schematic and layout; transient and post-layout simulation.
Design optimized circuit for achieving charge injection less than 2%
Validated functional characteristics using DRC, LVS, analog and digital tests.
• Design of R-String DAC
Schematic and layout generation, transient and post-layout simulations of the same.
Static performance figures like DNL, INL, gain, offset, thermal noise limitations are studied.
Validated functional characteristics by DRC, LVS, analog and digital tests.
• PCI arbitration using ASM chart
An arbitration logic is developed for Video conferencing applications which includes modules like
Video Grabber (VG), Video Coder/Decoder (VC/D), FireWire, CPU(Host), Advance Graphic
Port(AGP) and PCI arbiter using ASM chart.
The received video information is decoded by the Video Decoder module and sent through AGP to the
monitor for display. Also, FireWire serializes data and sends it over to the Video Coder for coding, and
the coded video information is sent to other Video Grabber modules through PCI.
PCI arbiter module is used to prioritize VG, VC/D, CPU (Host) and FireWire modules for efficient
performance of the system. Done by invoking logic for granting each of the modules’ requests.
High resolution color motion picture(1600x1200 pixels) processed using 100MHz PCI(X) bus.
Frame rate-30F/sec; frame period-33.3ns
Simulation, Synthesis, back annotation and place and route operations carried for the same.
• Design of on-chip Dual address ROM
Two address locations addr1 and addr2 accessed for data information. Outputs dout1 and dout2
corresponding to the given input information simultaneously.
ROM stores cosine and transpose of cosine matrices.
Two stage pipelining implemented to keep pace with dual RAM used in DCT Quantization techniques.
ROM size 8x64 i.e; among 8 possible address locations one can access two locations for data
simultaneously.
Verilog code developed, simulated, synthesized and optimized.
Back annotation and place and route functions carried on the optimized code.
• Implementing 16-bit Ripple Carry Adder
Schematic and layouts of the ripple carry adder developed by using transmission gates in Cadence
Virtuoso.
Validated functional characteristics by DRC, LVS, analog and digital circuits.
• Implementing Traffic Control Signaling Protocol using Verilog
Develop a protocol to effectively control traffic at an intersection of a main and a comparatively smaller
side road.
Verilog RTL code developed for all the possible states and also for the yellow blinking caution state
during nights.
Simulated using ModelSim. Synthesis done using Synplify and back annotated code tested and verified
against required operation.
• Evolution of LTE and LTE-Advanced
Detailed study of architecture, protocols and features.
Comparative study against WiMax standard.
Mathematical analysis of different performance values and deducing performance improvement over
previous standards.
• Implementing Multi Protocol label Switching (MPLS)
Studied the principles of MPLS
Implemented MPLS system in a laboratory environment with multiple users, analyzed the working and
advantages of MPLS over conventional network routing mechanisms.
Multiple users introduced into the network and data packets attached with a unique label are sent from
each of the users.
Switching is done based on the label information of each of the packets.
Programmed using C language.
Contact this candidate