Engineer Supply Chain

John Cawley

Email: *********@********.***

Address: ***** ****** ******* ****

City: Fremont

State: CA

Zip: 94539

Country: USA

Phone: 408-***-****

Skill Level: Director

Salary Range: $200,000

Primary Skills/Experience:

See Resume

Educational Background:

See Resume

Job History / Details:

John Cawley

47297 Rancho Higuera Rd

Fremont, CA 94539

(Cell) 408-***-****

*********@*****.***

OBJECTIVE Manufacturing or Component Engineering Leadership role.

PROFESSIONAL EXPERIENCE

Juniper Networks, Sunnyvale, CA 2010 present

Director, Front-end Test/ Mfg / Mech Engineering (re-org)

Manage WW Ops Engineering team (US, India and China) - 4 mgrs, 25 engineers

Technical disciplines: Front-end Test, Manufacturing and Mechanical Engineering

Responsible for all products companywide for both NPI and sustaining phases

Support product design centers in 3 different geographies (US, and India)

Planning and Qualification of New Factory Sites; 6 WW (US, China, Malaysia Mexico)

DFM, DFT, DFA, BOM structuring reviews

Own PCB layout and Mechanical design guidelines

Conduct semi-annual technology roadmap reviews with CM partners and PCB suppliers

Drive yield improvements and cost reductions across all products via value engineering

Reliability testing on L2 process for ASICs pkgs and other challenging component pkgs

Maintain technology roadmaps for PCB, Mechanical, and Thermal

Advise DE and Supply chain on PCB, Mech, and Therm sourcing selections

Qualified all mfg sites WW for Pb-free process, 6/6 RoHS

HDPUG and iNEMI consortiums members and participants

Implement best practices and processes across all regions

Planned and managed annual dept budget of ~$12M

Juniper Networks, Sunnyvale, CA 2004 2010

Director, Test/ Component / Manufacturing Engineering

Managed WW Ops Engineering team (US, India and China) - 4 mgrs, 35 engineers

Technical disciplines: Test, Mfg, Mechanical, Process and Component Engineering

End-to-end manufacturing, component and test for Enterprise products

Support all products from the Switch Security BUs in both NPI and sustaining phases

Support product design centers in 3 different geographies (US, India and China)

Planning and Qualification of New Factory Sites; 6 WW (US, China, Malaysia Mexico)

DFM, DFT, DFA, BOM structuring and Packaging reviews

Maintain all component technology roadmaps

Advise DE and Supply chain on primary and secondary component sourcing selections

Implement best practices and processes across all regions

Conduct quarterly score card and quality reviews with CMs and key comp suppliers

Quality and Reliability monitored through ORT and OOBA sampling on all products

Planned and managed annual dept budget of ~$15M

NetScreen Technologies, Sunnyvale, CA 1998 2004 (Acquired by Juniper in 2004)

Director, Tech Ops- Mfg Test, Quality and Component Engineering

Start-up opportunity. (IPO in Dec. 2001)

Assembled a team from scratch responsible for Test, QA, CE, Reliability and RMA repair

Calculated and published MTBF targets for all NetScreen products

Responsible for EMI and Safety compliance testing

Managed RMA FA and repairs in house for all products

Compiled pareto data from repairs and reviewed with design team weekly

Tested and recommend numerous design fixes, both HW and SW, to development team

Owned qualification and cost reductions on all 2nd source components

Conducted DFT reviews and developed mfg test programs for all products

Silicon Graphics (SGI), Mountain View, CA 1992 - 1998

Manager, Component Engineering

Managed component engineering company wide; 24 member team in 3 locations WW

Successfully consolidated all 3 divisional CE groups into one centralized organization.

(This served as the first working model for other functional groups within the company)

DVT for all CPU and Memory devices. Characterized key parameters and ranked

suppliers by margin to spec in our product environment

Built and tested large CPU, Memory and I/O configurations as part of qual process

Managed component AVL, 2nd source qualifications and cost reductions opportunities

MIPS Computer Systems, Sunnyvale, CA 1986 1992

Test engineer/ supervisor

Start-up opportunity. (IPO in Nov. 1989)

Developed test programs and test patterns to characterized MIPS RISC processors

Performed FIB repairs on CPU circuits as part of failure analysis process

Designed high speed DUT interface boards complete with TDR measurements

Developed new voltage vs. freq characterization algorithm that Teradyne later patented

Intel Corporation; Santa Clara, CA1982 1986

Product Test Engineer 1982 1986

Developed test programs and test patterns to characterize 80286 386 family of CPUs

Member of a 5 man task force team that brought next gen CPU products to production

Developed the first Hot Chuck at Intel used for testing wafers at high temperatures

EDUCATION B.S.E.E. - Cogswell College

Certified program languages: Basic, FORTRAN, Pascal, C, C++, Perl and Shell Script

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