Engineer Design

VINAY PANCHAL

*** * ********* ***, ***#C, Fullerton, CA-92831

Email: abo6mt@r.postjobfree.com Phone: 567-***-****

OBJECTIVE

Seeking a challenging career position in the field of Digital Design/Verification/Computer Architecture.

EDUCATION:

Master of Science in Electrical Engineering, California State University, Fullerton. May - 2012

Bachelor of Engineering in Electronics & Communication Engineering, Gujarat, India. June - 2009

PROJECTS:

Pipelined Matrix multiplier: RTL design and verification - Verilog, Synopsis Design Vision

Multiply 50X50 Matrix using two stages pipelined to improve throughput. De sign was synthesized and generated reports for area and timing.

Interface ADC, SRAM, LCD and FPGA: RTL design and verification - Verilog, Xilinx ISE

Designed hardware to Interface 16x2 LCD, 32K SRAM and 8 -bit ADC to FPGA and modeled finit state machine for writing data of ADC to

all address of SRAM and read back from SRAM and display it on LCD using FPGA.

Design& Perform Verification of Asynchronous FIFO: RTL design and verification System Verilog, Synopsis Design Vision

Designed an asynchronous 128byte-FIFO and performed synchronization between two different frequency domains. Advanced features of

System Verilog e.g. class, object, program block, clocking block, constraint base randomization, Assertion was used to thoroughly test the

design for different size of read/write transactions. Also verification concept of Interface was used to communicate between different

modules.

Design Single Cycle MIPS Processor: VHDL code Quartes II, Altera

Designed a different modules of Single Cycle MIPS processor.

Internal modules of FSDU (Frame Synchronization and Derandomization Unit): VHDL Code Quartes II, Altera

Internal modules are: Correlator input, Word rate clock generation for Imager and Sounder, Derandomization and generation of

PRBS (Pseudo Random Bits of Sequence).

Design a VHDL Code for Robertson Multiplier.

SKILLS:

Programming: Verilog, VHDL, C, Assembly language (x86/8051), C++, System Verilog, Perl

Computer Architecture: Pipelining, Intel QuickPath, MESI, Dragon update, Cache & Virtual memory

VLSI: RTL coding, ASIC design flow, Static timing analysis

Tools: Synopsys VCS Design Compiler & Analyzer, Xilinx ISE, MATLAB, LabView

Hardware proficiency: Schematic, PCB designing & Circuit Simulation using OrCAD 10.0

Equipment & board: Logic Analyzer, Oscilloscope, Function Generator

Microcontroller: 8051(ATMEL, Phillips, Analog Device), PIC 18F4550, PIC 16F877A

Compiler: MPLAB, Tasking EDE, Keil

EXPERIENCE:

R&D Engineer Masibus Automation and Instrumentation Pvt. Ltd., India. 01/06 - 06/09

Worked on a firmware to interface 7-segement LED Display, Keypad, ADC, DAC of High Speed Universal Transmitter with ADUC845

controller.

Worked on a Schematic and PCB layout.

Designed Hardware and Software for Downloader which loaded Hex files from computer to microcontroller through USB using PIC18F4550

and PIC16F877A.

R&D Engineer Indian Space Research Organization (ISRO). India. 07/09 - 07/10

INSAT 3D has two meteorological Payloads like IMAGER and SOUNDER operating simultaneously and the images are taken by scanning the

earth and its atmosphere by means of scan mirrors in each payload.

I designed the software that finds the Fast Scan Present Position (FSPP) and Slow Scan Present Position (SSPP) for these Payloads using

Labview.

RELATED COURSE WORKS:

System Verilog, Verilog, VHDL Multiprocessor Cache Coherency RTL Design, Verification, Synthesis

Setup & Hold Time, Design Reports x86 Architecture, Programming Interface PCI, Cache, Virtual Memory, Arbbitration

Snooping, Pipelining Advanced Digital Logic Designing Microprogramming and Embedded Microprocessors

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