Homa Alemzadeh

Ph.D. Student *** Coordinated Science Laboratory

ECE Department 1308 W Main St, Urbana, IL 61801

University of Illinois at Urbana-Champaign Tel: 217-***-**** (Office)

http://users.crhc.illinois.edu/alemzad1/ E-mail: abo63i@r.postjobfree.com

Research Interests

? Design for Dependability

? System Level Design and Synthesis

? Trusted Hardware and Secure Coprocessor Design

? Digital System Testing and Design for Testability

Education

Ph.D. Student in Computer Engineering, Jan. 2009 Present, (Expected 2012)

University of Illinois at Urbana-Champaign (UIUC), Urbana, Illinois.

Thesis Advisor: Prof. Ravishankar Iyer, GPA: 4.00/4.00

M.Sc. in Computer Architecture, Nov. 2008,

University of Tehran, Iran.

Thesis Topic: Testable SystemC TLM Primitives

Thesis Advisors: Prof. Zainalabedin Navabi, Prof. Paolo Prinetto, GPA: 18.65/20.00

B.Sc. in Computer Engineering Hardware, Jul. 2005,

University of Tehran, Iran.

Final Project: Evolutionary Design of Digital Logic Circuits using Genetic Algorithms

Advisor: Prof. S. Mehdi Fakhraei

Work Experience

Graduate Research Assistant, DEPEND Group, Jan. 2009Present, UIUC, Urbana, IL.

? Design of a trustworthy reconfigurable processor for health monitoring applications.

? Programming Graphics Processing Units (GPUs) for high performance cryptography.

Research Assistant, CAD Research Group, Nov. 2005 Nov. 2008, University of Tehran, Iran

? System Level Design for Testability

? Research on methods of design for testability at Transaction level and

development of testable SystemC TLM channel models.

? Synthesis of Testable TLM primitive channels and test coverage evaluation.

? System Level Design for Dependability and Reliability Analysis

? Development of a SystemC Transaction Level Simulator for Fault-tolerance and

Reliability Analysis of Network on Chip Architectures.

? Design and implementation of a SystemC TLM NoC Library for modeling and

simulation of mesh-based NoC architectures.

? System Level Design and Synthesis

? Contributing to the development of a component-based ESL design environment for

simulation and synthesis of SystemC Transaction Level Models.

? Contributing to the design and implementation of a PCI Bus model in SystemC TLM.

? Implementation of code optimization techniques in a VHDL to SystemC conversion

tool for enhancing the simulation time of SystemC models.

Hardware Engineer, Arman Optimized Systems Corp., July 2003 August 2004, Iran

? Hardware Design and Implementation, PCB Design, and Test of a FPGA-based PCI Bus

Interface Card (PCI-GPISIRelay-E) for Industrial Automation Systems.

Selected Course Projects

? Hardware implementation of Trusted Time-stamping, Design of Reliable Systems

and Networks course project, University of Illinois at Urbana-Champaign, Fall 2009.

? Hardware design, implementation, and Synthesis of 256-bit AES

Encryption/Decryption on Altera FPGA/NVIDIA GPU, Computer Security course

project, University of Illinois at Urbana-Champaign, Fall 2009.

? Implementation of 1024-bit RSA Encryption on NVIDIA GPU using CUDA framework,

Programming Massively Parallel Processors course project, University of Illinois at

Urbana-Champaign, Spring 2009.

? Implementation of full scan, partial scan, BIST and boundary scan test for an

educational processor, Digital System Test and Design for Testability course

project, University of Tehran, Spring 2007.

? Design, VHDL implementation and Synthesis of a Reconfigurable FIR Processor Core,

High Level Design and Implementation of a Network-on-chip (NoC) Infrastructure,

and Design, VHDL implementation and Synthesis of a 32 channel Voice filter system

with ST-BUS input and outputs, Digital System Design with VHDL Hardware

Description Language course project, University of Tehran, Fall 2006.

? Verilog Implementation, Simulation, Synthesis and Extracting Layout of a Mirror

Adder, an Array Multiplier, a FIR filter and Pipeline MIPS processor, VLSI course

project, University of Tehran, Fall 2003.

Technical Skills

Hardware Languages VHDL, Verilog, SystemC (TLM, RTL).

Programming Languages C/C++, CUDA for GPU, Java, x86 Assembly.

Technical Tools ModelSim, Altera Tools, Xillinx ISE, Leonardo, Synopsys,

Tanner Tools (LEdit/SEdit), HSpice, Protel/Design Explorer,

SimpleScalar.

Operating Systems Windows and Linux.

Publications

[

DESIGN & TEST INTERNATIONAL SYMPOSIUM (EWDTS 08), Lviv, Ukraine, October 2008.

[3] Homa Alemzadeh, Stefano Di Carlo, Alberto Scionti, Paolo Prinetto, Zainalabedin

Navabi, Functional Testing Approaches for BIFSTable tlm_fifo, In Proc. of IEEE

International High-Level Design Validation and Test Workshop 2008 (HLDVT'08),

Nevada, US, November 2008.

[4] Fatemeh Refan, Parisa Kabiri, Homa Alemzadeh, Paolo Prinetto and Zainalabedin

Navabi, Application Specific Configuration of a Fault-tolerant NoC Architecture, In

Proc. of 11th Biennial Balitic Electronics Conference (BEC 08), Estonia, October 2008.

[5] Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Zainalabedin Navabi and Paolo

Prinetto, Plug & Test at System Level via Testable TLM Primitives, In Proc. of

International Test Conference (ITC 08), Santa Clara, US, October 2008.

[6] Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto and Zainalabedin

Navabi, Reliability in Application Specific Mesh-based NoC Architectures, In Proc. of

14th IEEE International Online Testing Symposium (IOLTS 08), pp. 207-212, Rhods,

Greece, July 2008.

[7] Homa Alemzadeh, Fatemeh Refan, Paolo Prinetto and Zainalabedin Navabi, High-

level Analysis for Reconfiguration of a Fault Tolerant Mesh-based NoC Architecture

Using Transaction Level Modeling, In Proc. of 5th IEEE EAST-WEST DESIGN & TEST

INTERNATIONAL SYMPOSIUM (EWDTS 07), pp. 256-261, Yerevan, Armenia, Sep. 2007.

Technical Talks

? Facilitating Testability of TLM FIFO: SystemC Implementations 6th IEEE EAST-WEST

DESIGN & TEST INTERNATIONAL SYMPOSIUM (EWDTS 08), Lviv, Ukraine, October

2008.

? Code Optimization for Enhancing SystemC Simulation Time 6th IEEE EAST-WEST

DESIGN & TEST INTERNATIONAL SYMPOSIUM (EWDTS 08), Lviv, Ukraine, October

2008.

? SystemC Studio: Translation for TLM Combined Simulation and Synthesis, University

th

Booth of University of Tehran, 11 Design, Automation and Test in Europe

Conference (DATE 08), Munich, Germany, 10-14 March 2008.

? An NoC Test Strategy Based on

Flooding with Power, Test Time

and Coverage Considerations, On behalf of the Authors, 21st International

Conference on VLSI Design (VLSI Design 2008), Hyderabad, India, 4-8 January 2008.

th

? UT SystemC Studio Tool, University Booth of University of Tehran, 10 Design,

Automation and Test in Europe Conference (DATE 07), Nice, France, 16-20 April

2007.

Teaching Experience

Feb. 2008 Nov. 2008, Teaching Assistant, ECE Department, University of Tehran, Iran

? Digital Logic Circuits Laboratory. Responsible for conducting lab sessions, teaching

prerequisite concepts for experiments, preparing quizzes and grading.

Nov. 2007 Feb. 2008, Teaching Assistant, ECE Department, University of Tehran, Iran

? Advanced Computer Architecture Course. Responsible for preparing computer

assignments and grading.

Sep. 2007 Feb. 2008, Teaching Assistant, ECE Department, University of Tehran, Iran

? Digital System Design with VHDL Hardware Description Language Course.

Responsible for conducting extra course sessions, teaching part of concepts on behalf

of the instructor, and preparing and grading computer assignments.

Sep. 2006 June 2007, Teaching Assistant, ECE Department, University of Tehran, Iran

? Digital Logic Circuits Laboratory. Responsible for conducting lab sessions, teaching

prerequisite concepts for experiments, preparing quizzes and grading.

Feb. 2005 June 2005, Teaching Assistant, ECE Department, University of Tehran, Iran

? Computer Architecture Course. Responsible for conducting discussion sessions and

grading computer assignments.

Feb. 2004 June. 2004, Teaching Assistant, ECE Department, University of Tehran, Iran

? Computer Architecture Laboratory. Contributing to organizing the laboratory,

Responsible for preparing laboratory material, Conducting lab sessions and grading.

Professional Activities

th IEEE EAST-WEST DESIGN & TEST INTERNATIONAL SYMPOSIUM

(EWDTS 08), Lviv, Ukraine.

? Member of Registration Committee of 5th IEEE EAST-WEST DESIGN & TEST

INTERNATIONAL SYMPOSIUM (EWDTS 07), Yerevan, Armenia.

? Leader of Student Organizing Committee of First International Caspian Design and Test

Workshop (iCDT 07), University of Tehran, Iran.

? Volunteer Member of Organizing Committee of Nano-Electronics Lecture Series, CAD

Research Group, University of Tehran, Iran.

? Volunteer Member of Organizing Committee of Fourth Iranian Student Conference on

Electrical Engineering (ISCEE 01), Iran.

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