Engineer Design
Resume:
Joel McNees
Email: *********@********.***
Address: **** ***** **
City: Carrollton
State: TX
Zip: 75007
Country: USA
Phone: 469-***-****
Skill Level: Experienced
Salary Range: 140
Willing to Relocate
Primary Skills/Experience:
See Resume
Educational Background:
See Resume
Job History / Details:
JOEL MCNEES
3964 VALEZ DR; CARROLLTON, TX, 75007
*********@********.***
PROFILE
Principle Engineer experienced in all aspects of ASIC design, with main focuses on DFT, STA and Place & Route. Successfully taped-out multi-million gate designs collaborated with engineers and customers on three continents.
PROFESSIONAL EXPERIENCE
RENESAS ELECTRONICS IRVING, TEXAS
Principal Design Engineer/Automotive Design April 2010 - Present
* Worked with Renesas Japan to update DFT flow for ASSP designs at Renesas Dallas, reducing area for SCAN. Updated DFT environment to work for Mentor (MBIST) and Synopsys (SCAN).
* Created STA timing closure environment for Renesas 90nm process using Primetime for timing verification and TimeCraft for hold fixes and power reduction. STA environment includes AOCV, MCMM.
* Modified DFT flow to reduce MBIST power by disabling unused segments of the clocktree not needed for MBIST. Verified power reduction using PrimeTime PX with SPEF from layout data and SAIF files from Verilog simulations.
* Wrote Perl script to convert tester fail log into format to be read by Synopsys TetraMax, improving yield of at-speed transition delay patterns.
NEC ELECTONICS DALLAS, TEXAS
Principal Design Engineer/Automotive Design January 2006 - April 2010
* Collaborated with NEC design center in Germany to provide DFT, STA and Place & Route support for ASSP designs used in Europe and the United States. Flow included use of LogicVision for DFT and Cadence for Place & Route. Successfully taped-out five ASSP designs during that collaboration.
* Worked with NEC chip designers to create and debug LogicVision ROMBIST insertion for NEC on-chip FLASH.
* Created MCMM Place & Route flow, specifically for NEC Dallas, using Sierra Pinnacle for Automotive designs. Place & Route had previously been done only at NEC Japan. Used this flow to successfully tape-out automotive air bag ASSP.
Design Engineering Manager/ASIC Design January 2000 - January 2006
* Managed the successful taped-out of multi-million gate designs for high profile customers such as Intel and Nortel.
* Created Hierarchical Place & Route flow using four different layout tools (Cadence Encounter, Synopsys Physical Compiler, Sierra Pinnacle, NEC internal tools). Pushed technology rated for 250Mhz operation to 400Mhz, meeting Intel's requirements of low power and high performance. Flow included hierarchical floorplanning, OCV, MCMM, block reuse and high-speed low EM clocks.
* Awarded best design presentation at NEC design conference for work on Intel Co-Processor.
* Worked with EDA vendors and managed NEC team members to develop hierarchical layout flow with area IO capabilities to handle multi-million gate and high pin out designs. Successfully taped-out 20 Million gate 1000 pin Telecommunication ASIC using this flow.
* Conducted and gave presentations for customer design kick-off meetings.
STMICROELECTRONICS CARROLLTON, TEXAS
Staff Design Engineer/Broadband ASIC Design January 1996 - January 2000
* Project Manger for Scientific Atlanta Set-top Box ASICs. Tasks included: Hierarchical Place & Route, test pattern generation, coordinating with ST team members to complete DRC/LVS and Reticle generation and interfacing with customers on all design related activities.
* Worked with management to win other Scientific Atlanta projects.
* Wrote Perl script to place data path structure for Sun Sparc core in Cadence floorplan tool, increasing frequency of Sparc data-path.
* Wrote Perl script to automate the merger of hierarchical SDF into a single SDF.
AMI SEMICONDUCTORS POCATELLO, IDAHO
Design Engineer/Digital ASIC Design January 1991 - January 1996
* Digital project engineer for Gate Array and Standard Cell designs.
* Verified functionality of customer's designs before and after layout by simulating all vectors over five process corners.
* Performed over sixty FPGA-to-ASIC and ASIC-to-ASIC conversions.
NATIONAL SEMICONDUCTOR WEST JORDAN, UTAH
Engineering Assistant Internship June 1988 - January 1991
* Characterized high-voltage MOS field-effect transistors and other semiconductor devices.
EDUCATION
UNIVERSITY OF UTAH SALT LAKE CITY, UTAH
BS Electrical Engineering/Minor Math
* Emphasis: VLSI Design, Digital Computer Systems and Devices
* Senior Thesis: Short channel effect in MOS field-effect transistors
ADDITIONAL SKILLS
* Computer Languages: Verilog HDL, Perl, TCL, LISP, C
* Simulators: VCS, NCVerilog
* Synthesis: Synopsys Design Compiler, Cadence RTL Compiler
* DFT: Mentor Tessent (previously LogicVision), Synopsys Design Compiler/TetraMax/PowerFault
* Place & Route: Mentor Olympus (previously Sierra Pinnacle), Cadence Encounter
* STA: PrimeTime, TimeCraft
* Power Analysis: PrimeTime PX
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