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Software Design

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Austin, TX

Posted:

October 16, 2012

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Consultant (Specman)

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Resume: Design Verification Consultant (Specman)

Veritec

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Posts: n/a

10-10-2003

Chris Starr

SPECIAL SKILLS

VLSI CAD TOOLS

Cadence, Verisity, Viewlogic, VCS, MTI, Verilog-XL, VHDL, Speedsim, Specman,

Denali, SKILL, Composer, ViewDraw, Smartmodels, Hardware Models

TELECOM

Sonet, STS-1, STS-3, STS-12, DS1, DS3, VT 1.5

AVIONICS

Fuel Measurement/Management Systems, Full Authority Digital Engine Controls,

Electronic Flight Instrumentation Systems

METHODOLOGIES

DO-178A, MIL-STD-2167A, OOD, OOP

LANGUAGES

C++, Pascal, PLM, FORTRAN, FORTH, MAILSAIL, MIL-STD-1750A (Fairchild 9450),

80x86, 68000 Assembler

COMPILER TOOLS

LEX, Perl, YACC, FLEX, BISON (specialist in application specific compilers)

OPERATING SYSTEMS

UNIX, Solaris, AIX, VAX/VMS, MS-DOS, HP/UX

HARDWARE

PC, VAX, Sun, HP-700, RS6000COMMUNICATIONS

PCI 2.2, PCI-X, GPIB, MIL-STD-1553, ISDN BRI, ARINCPROFESSIONAL EXPERIENCE

MAY03-SEP03 Intel, ICG Division, Austin, Texas. Responsible for the

implementation of several functional coverage plans for the host interface

of a LAN access chip. Functional coverage was implemented using Verisity's

Specman language. The simulation platform was MTI using Verilog design

components. Interfaces of interest include PCI, PCI-X 1.0b, PCI-Express and

TCP/IP. The hardware platform was an X86 based PC running Redhat Linux.

JAN03-MAY03Inrange Technologies, Lumberton, New Jersey. Helped complete

verification of a fibre channel switch platform. The test bench was written

using Verisity's Specman language. The simulation platform was MTI using a

mix of Verilog and VHDL design components. Duties included test bench

enhancements and system-level verification of the design. The hardware

platform was an X86 based PC running Redhat Linux.

FEB01-JUL02Agere Systems, Austin, Texas. Responsible for the design and

implementation of simulation test bench drivers to configure a network

processor chipset. The test bench was implemented using Specman e-code and

Denali memory models. Some highlights of the configuration code include:

* Register/memory access via PCI cycles or PCI DMA transfers or RTL

hierarchy. Access via RTL hierarchy would allow configuration to be

completed in zero-time. Configuration access mode could be switched with a

run time flag (no test case changes).

* High-level register/memory access interfaces to simplify test case

writing. The test case writers would interface with abstract system-level

data structures instead of low-level bits and bytes.

* Automated configuration of complex memory architectures (FCRAM, QDRRAM).

Also worked as a general resource for netlist bring-up and test case

debugging.

AUG99-FEB01 Analog Devices/Intel Joint Development Project, Austin, Texas.

Responsible for the design and implementation of a simulation test bench for

a new DSP core being developed jointly by ADI and Intel. The test bench was

implemented in Verilog (XL/VCS/NCVLOG). Some highlights of the test bench

include:

* Ability to load program code into L2-memory and instruction-cache memory.

* Ability to load program data into L2-memory and data-cache memory.

* Integration of an architectural reference model for the DSP core into the

test bench.

* Automated checking of register value changes using data from the reference

model.

* Implementation of the entire 4GB L2 memory space using a sparse memory

model.

* Automated checking of program counter changes due to interrupts and

exceptions.

* Very fast instruction execution (approximately 350 instruction per second

using compiled simulation).

* Scripting language to control core inputs and to test core outputs

(resets, clocks, interrupts, exceptions, configuration pins, etc.).

Also worked on a chip being developed solely by ADI using the DSP core.

This chip included the DSP core, a bridge from the core to several Amba

buses (high and low speed), L2-memory, SDRAM controller, SRAM controller and

various on-chip Amba bus peripherals (UART, SPORT, SPI, DMA engines, etc.).

My work involved real-time troubleshooting of the test bench and netlist to

enable test case writing to continue.

MAR99-AUG99Compaq, Austin, Texas. Responsible for the block-level

verification of a PCI-X megacell. The megacell converted PCI-X transactions

to and from a proprietary on-chip interface bus. Developed test plans,

coded a random PCI-X transaction generator for stress testing the megacell

(using Verilog-XL), implemented test cases, and helped supervise a group of

co-op students at Texas A&M also working on the project.

NOV97-MAR99AMD, Austin, Texas. Responsible for the system-level

verification of a system-on-a-chip consisting of an x86 microprocessor core,

PCI host bridge, SDRAM controller, ROM controller and various PC/AT

compatible devices (8237 DMA, UARTs, RTC, PIC, etc.). The system test bench

environment was constructed using Verisity's e-language based verification

tool (Specman) integrated with Verilog-XL based bus function models (PCI

bus, x86 bus, SDRAM devices, ROM devices, etc.)

NOV96-OCT97IBM, Microelectronics Division, Research Triangle Park, North

Carolina. Responsible for the system-level verification of a 1100K gate

set-top-box ASIC. Developed bus functional models for several internal

interconnect buses using C++. These models would interface to SpeedSims'

cycle-based simulator through the standard PLI interface. Developed and

implemented test suites to verify the connectivity of the microprocessor

core, cross-bar switch, MPEG-2 video and audio decoders, DRAM, SRAM, SDRAM

and other off-chip interfaces.

JUN 95-NOV 96Cisco Systems, Research Triangle Park, North Carolina.

Responsible for the system-level verification of the Cisco 7200 series

router. Developed verification tools and turnkey regression test suites for

three high-density printed circuit cards. Verification was done using the

Cadence Verilog-XL simulator, Synopsys SmartModels and hardware models.

System-level regression test suite was written primarily in Synopsys PCL

code. A Verilog behavioral model was created to simulate the bus activity

generated by various port adapter cards which plug into the router chassis

via a PCI bus interface.

Also developed a chip-level test bench for an ASIC that bridges token-ring

frames from a proprietary switching bus to a PCI bus. The test bench was

developed using Specman (a next-generation verification tool from Verisity).

This tool was used to automatically generate token-ring frame stimulus and

verify that the frame data was passed correctly through the chip based on

the destination address, RIF, SNAP and DSAP fields.

FEB94-JUN95Alcatel Network Systems, Raleigh, North Carolina. Developed

drivers and monitors (Verilog-XL) to generate and analyze STS-1, STS-3 and

STS-12 stimulus patterns for an ASIC chipset being used in Alcatels' next

generation SONET switches. These drivers/monitors were integrated into a

user-friendly test bench to expedite system- level verification of the

chipset.

FEB92-FEB94 IBM, Network Systems, Research Triangle Park, North Carolina.

Developed behavioral models (Verilog-XL) to simulate the system-level

environment of a full motion video co-processor for an IBM-PC graphics

adapter card. Responsible for the implementation of full chip simulation

scenarios to test capabilities of the co-processor which included scaling,

cropping, dithering and YUV-RGB conversion. Behavioral models generated for

system level functions included VRAMs, NTSC and compressed video data

sources, host computer data source, memory bus arbitration module and

assorted analysis modules to track data flow inside and outside of the chip.

NOV88-FEB92Honeywell, Commercial Flight Systems, Phoenix, Arizona.

Designed, coded and tested software to perform branch and code coverage

analysis on an electronic flight instrumentation system for the MD-11

commercial aircraft. This package consisted of: a pre-processor (VAX C) to

determine the possible branches taken by the flight software; a

mid-processor (80386 Assembler) to record the actual branches taken; a

post-processor (VAX C) to compare the possible with the actual branches and

produce a coverage report detailing any unexecuted code or branches. Also,

developed software to provide symbology for 80386 emulation on an HP9000

workstation. Also, developed software to facilitate functional testing of

the flight software.

Developed a unique testing tool which allowed component integration-level

tests to be generated automatically from individual component-level tests

resulting in a dramatic reduction in man-hours required to certify the

flight software.

Developed a code-scanning compiler to verify the integrity of manually

entered data-dictionary information with procedure/variable references from

the source code.

FEB88-AUG88Hamilton Standard, Windsor Locks, Connecticut. Designed, coded

and tested software to perform diagnostic testing on Full Authority Digital

Engine Controls (FADEC) for large military jet engines. Software was

written in Pascal for an HP9000.

Oct87-Feb88AT&T Information Systems, Denver Colorado. Designed, coded and

tested software to perform diagnostic testing on ISDN BRI compatible

terminals for the System 85 PBX.

OCT86-OCT87Simmonds Precision, Vergennes, Vermont. Designed, coded and

tested software to perform diagnostic testing on a fuel measurement and

management system for military aircraft. This package consisted of software

running in the flight computer (MIL-STD-1750A or Fairchild 9450) to perform

functional testing of the hardware and software running on an IBM-PC

(Microsoft C & 8088 Assembler) to control test execution and error logging.

Challenges of this assignment: a wide variety of communications interfaces

(RS-232, IEEE 488, MIL-STD-1553); customized interrupt handlers (UART,

keyboard, timer); a wide variety of test equipment (HP6032A Power Supply,

LORAL SBA 100A, Control Systems Research MICRISTAR). Extensive

documentation (MIL-STD-2167A) was produced to satisfy the standards and

procedures of military contracts. Also, developed a Software Source Control

System to help maintain customized releases of this package.

FEB86-MAY86General Electric, Co., Somersworth, New Hampshire. Made bug

fixes/enhancements to EPROM burning software (FORTRAN 77) used by GE to

program their line of demand recording meters. These enhancements included

the ability to handle 256K EPROMs, validation testing features and changing

file allocation from static to dynamic.

FEB85-FEB86Versatile Systems, Inc., Belmont, California. Designed, coded

and tested software to translate the database of one PC-based architectural

drawing program to another. Also, developed a customized PILOT language

interpreter.

MAR82-FEB85VLSI Technology, Inc., San Jose, California. Major contributor

to the cell compiler project. This is a library of customized hardware

components generated by a collection of software elements called cell

compilers. These cells, by allowing a logic designer to create flexible

building blocks (i.e., registers, counters, ALUs), can significantly reduce

the time required to develop an ASIC. Consultant for several custom chip

projects: Macintosh Computer for Apple, Atari home video game, Cable TV

descrambler, Display Controller for a portable PC. These projects

encompassed all aspects of VLSI chip design from schematic entry/logic

simulation to cell layout/chip composition.

JUN81-MAR82Hewlett Packard, Disc Memory Division, Boise, Idaho. Designed,

coded and tested software to automatically generate PLAs for VLSI chips.

This package consisted of: a compiler to convert a high-level language

description of the finite state machine behavior to truth tables; a logic

minimizer to reduce the truth tables; a PLA generator to convert the truth

tables to mask geometry.

SEP73-JUN75South Burlington High School, South Burlington, Vermont.

Designed, coded and tested software to perform class scheduling, produce

class lists and to maintain attendance records for the school.

EDUCATION

JUNE 1981 Master of Science in Electrical Engineering program, Dartmouth

College, Thayer School of Engineering, Hanover, New Hampshire. One year

credit toward degree.

JUNE 1980 Bachelor of Science in Computer Science with a minor in electrical

engineering, Michigan State University, East Lansing, Michigan. Graduated

cum laude.

PATENTS United States Patent #6,052,745, System for asserting burst

termination signal and burst complete signal one cycle prior to and during

last cycle in fixed length burst transfers.

PUBLICATIONS

[1] Cell Compilers vs. Standard Cell Design, Custom Integrated

Circuits Conference, Rochester, NY, 1984.

[2] Cell Layout Compilers Simplify Custom IC Design, EDN, September

15, 1983.

[3] Automatic PLA Generation, Hewlett Packard VLSI Conference,

Corvalis, Oregon, 1981.

Veritec

valdonio

Junior MemberNov 2010

Posts:

11-15-2010

Dear Mr. Starr,

I wonder whether you are the same Chris Starr that wrote an excellent article on the

Daimler Benz DB engines on Aeroplane Monthly in May 2005.

If so, I would ask you to help me in my research on the WW2 Italioan aircraft. As you

certainly know, the DB601A engine was built in Italy as the Alfa Romeo RA.1000 RC.41,

rated at 1,175 cv (cv is the same as PS in Germany).

According to the very limited info contained in the Macchi C.202 flight manual, the

engine was rated for a normal TO power at 2400 rpm and 1.35 kg/cm2 MP, and an emergency

power at 2400 rpm and 1,45 kg/cm2 (limited to 1 minute use): according to your article,

this is more than the standard DB601A-1 and corresponds with the DB601N rating.

Furthermore the Italian manual requires fuel of 89-91 octane.

So, in reality which one was the version on which the Italian engine was based?

Finally, would you have a complete set of power xcurves for this engine (or for the

DB601A-1 and DB605A?

Thank you in advance for your help

Giulio Valdonio

Milano, Italy

valdonio

Find More Posts by valdonio

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