Design Electrical
Resume:
Yang Liu
Gradute Student at University of Southern California
Location
Los Angeles, California (Greater Los Angeles Area)
Industry
Electrical/Electronic Manufacturing
.
Yang Liu
Contact Yang Liu directly
Yang Liu's Overview
Current
ASIC Design Intern at Marvell
Education
University of Southern California
Beijing University of Posts & Telecommunications (BUPT)
Connections
33 connections
Websites
Yang Liu's Summary
To pursue a challenging full-time position in digital design field.
Specialties:
- ASIC design/verification/Synthesis using Verilog/SV
- Perl, C++ and Matlab programming
- ASIC timing/power analysis, and optimization
- Computer Architecture
- Communication Theory/DSP
Email Address: abo03w@r.postjobfree.com
Yang Liu's Experience
ASIC Design Intern
Marvell
Public Company; 5001-10,000 employees; MRVL; Semiconductors industry
May 2012Present (4 months) Marvell Ln. Santa Clara, CA
Intern position in CORE IP Group. (LR-WPANs Zigbee IC Design)
Yang Liu's
Education
University of Southern California
Master of Science, Electrical Engineering
20112013 (expected)
Grade: 4.0/4.0
Beijing University of Posts & Telecommunications (BUPT)
Bachelor of Science, Optical Information Science and Technology
20072011
Grade: 3.55/4.0
Graduate Thesis: Performance Study of OFDM on Multimode Fiber (Excellent Graduation
Thesis of BUPT).
Yang Liu's Courses
Bachelor of Science, Optical Information Science and Technology
Beijing University of Posts & Telecommunications (BUPT)
Communication Theory
DSP
Signal and System
Optical Communication Theory
Master of Science, Electrical Engineering
University of Southern California
MOS VLSI Circuit Design (EE477L)
Computer Systems Organizations (EE457)
VLSI System Design (A) (EE577A)
VLSI System Design (B) (EE577B)
Directed Research (EE590)
Yang Liu's Projects
Network-on-Chip 2D mesh router
February 2012 to June 2012
Team Members: Yang Liu
Designed the router for CMP SOC using RTL Verilog and compiled adequate testbench.
Completed physical implementation Synthesis, Formal Logical Equivalency, Static Timing
Analysis, P&R.
Digital Image Uniform Noise Attenuation
May 2012 to June 2012
Team Members: Yang Liu
Awarded the designer contest winner, Clock Period * Area is almost half of the 2nd
group.
Creatively designed a pipelined methodology to read 4 data from and write 1 data to SRAM,
achieved noise attenuation of 1 pixel only in one clock circle, (1/6 of the original
specification).
Initiated to Combine CS(save)A, CS(select)A, CLA, Manchester Carry Chain to achieved 1.0
ns delay of 4 12bits data adding with load.
Full custom layout design of 1k SRAM, other data pathes and control logic.
Two-Direction Digital Timer Design
November 2011 to January 2012
Team Members: Yang Liu
Awarded the designer contest winner among 73 groups based on Clock Period * Area .
Design is adopted and introduced in course EE577a.
Creatively designed a counter instead of adder/subtractor to minimize the delay on the
critical path.
Redesigned the FSM (reduced two register) to save the logic and the layout s area.
IEEE single-precision floating-point unit
November 2011 to January 2012
Team Members: Yang Liu
Designed a mechanism to accomplish floating-point calculation based on Verilog HDL.
5-Stage-Pipeline Mips CPU Design
September 2011 to December 2011
Team Members: Yang Liu
Designed a 5-stage simple pipelined processor to support in order execution of simple
instructions taking care of RAW and Branch hazards.
Effective Trojan Insertion Method
October 2011 to June 2012
Team Members: Yang Liu
Invented a logic effort based method to minimize the delay and area change as a Trojan
designer.
Proposed a new challenge to the Trojan detector as the delay has been optimally minimized
with Prof. Gupta.
Performance Study of OFDM on Multimode Fiber
August 2008 to June 2011
Team Members: Yang Liu
Excellent graduation Thesis of Beijing University of Posts & Telecommunications.
Conducted optical modulate and demodulate simulation on Optisystem, using component as
MQAM, OFDM, (D)FFT, M-Z inter-ferometer, etc.
Developed a method to judge the O-OFDM MIMO system performance (coordinate graph, eye
pattern).
LR-WPANs Zigbee IC Design
May 2012 to Present
Team Members: Yang Liu
HDL implemented the DSP part of PHY_TX (Spreading, Pulse shaping, multistage
interpolation).
Assisted the verification of the PHY_TX and the whole chip using UVM.
CRC and AES encipher verification on CM0 CPU.
Yang Liu's Skills & Expertise
ASIC
System Verification
Verilog
system verilog
UVM
C
C++
Perl
Unix
Cadence Virtuoso
Synopsys Design Compiler
Hspice
Primetime
Conformal LEC
P&R
LVS
DRC
Matlab
Vim
Yang Liu's Additional Information
Websites:
Groups and Associations:
ASIC (Application Specific Integrated Circuit) Community
ASIC / VLSI Experts
ASIC Design & Verification
ASIC, FPGA, SoC Engineers
Broadcom Corporation
Chinese Entrepreneurs Organization
Entry Level Engineers
Entry Level Engineers - Electrical / Computer
H1B Jobs
Oracle Jobs
SOC Forum - ASIC/FPGA/IP/EDA Engineers, Contractors, Execuitives
Semiconductor - VLSI
Semiconductor Jobs North America
Top 10 EDA Problems
USC - Silicon Valley
USC Career Center
USC Trojan Network
USC Viterbi Alumni
Viterbi School of Engineering
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