Engineer Electrical
Resume:
Midlothian, VA *****
******@**.***
Bradley J. Heath
Experience
September 2006 – December 2008
Qimonda Richmond, VA
Failure Analysis Engineer-
Correlated electrical fail signatures to physical failures on trench capacitor DRAM
memory chips
Managed the failure analysis lab queue by determining job priority and writing
passdown for night-shift PFA technicians
Managed the work of 10 technicians
Traced the cause of the failure to a particular process module
Presented PFA results at yield meetings and excursion meetings
Participated in Six-Sigma task force to decrease yield excursions
Published technical reports detailing failure analysis process and conclusions
October 2004- September 2006
Cree Durham, NC
Test Engineer – Silicon Carbide Power Device Research Group
Device characterization of SiC discrete power semiconductor devices for government
military research contracts
Measured DMOSFET semiconductor parameters for PSPICE model and application
notes
Designed test fixtures
Designed a switch-mode boost converter circuit to illustrate the improved efficiency
of silicon carbide power switches
Performed reliability measurements of SiC DMOSFETs including power cycling,
gate oxide stress, and avalanche energy tests
March 2001-August 2002
Dominion Semiconductor /Micron Technology Manassas, VA
Failure Analysis Engineer
Performed electrical device characterization on Flash and DRAM memory chips
using semiconductor analyzers, capacitance meters, probe stations, and other
electrical test equipment.
Visually characterized failing mechanisms in memory chip using chemical and
mechanical deprocessing techniques, SEM, FIB, and other PFA tools
Analyzed MOSFET parametric test data, field bit maps, and yield sort data
Presented results of electrical characterization/physical failure analysis to device
engineers and process engineers to aid in yield improvement
May 2000-August 2000
Kemet Electronics Simpsonville, SC
Electrical Engineer Intern
Drafted PLC panels, I/O addressing, and enclosures using AutoCad
Established priority charts for capacitor manufacturing tools
January 1999-May 1999
Analog Devices Greensboro, NC
Co-op Student
Trouble-shooting circuit boards
Responsible for chip failure analysis tests
Education
August 1996-December 2000
Clemson University Clemson, SC
B.S., Electrical Engineering. 3.0 GPA
August 2002- May 2004
Virginia Tech Blacksburg, VA
Completed M.S. degree in Electrical Engineering, 3.2 GPA
Assisted advisor in research studying the influence of base layer composition and
alloy grading on GAIN base HBTs
Relevant coursework: Electronics Packaging, Microwave Engineering, LED
Semiconductor Devices, Semiconductor Processing, MOS Device Theory, Digital
Integrated Circuit Design, VLSI Design, Design of Experiments, Power Electronics,
Semiconductor Device Modeling, Materials Characterization
Skills
Computer: Windows, Unix, Excel, PowerPoint, Cadence, PSPICE, HSPICE,
MathCad, ICS Metrics, wafer field bit maps
Electrical Characterization: Micro-probing, bench testing, Tektronix high power
curve tracer, Keithley 4200 semiconductor analyzer, Agilent capacitance meter,
switch matrix, liquid crystal technique, light emission microscopy, Tektronix/
LeCroy digital oscilloscopes, pulse generator, power supplies
Physical Failure Analysis: SEM, FIB, EDX, optical microscopy, laser marking,
plasma etching, chemical deprocessing
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