Design Engineer Project

ANUSH N. MOHANDASS

**** * ******** ***, *** ****, Chicago, IL 60605

Mobile: 408-***-****, E-mail: ********@************.***

EDUCATION

THE UNIVERSITY OF CHICAGO BOOTH SCHOOL OF BUSINESS Chicago, IL

Master of Business Administration Sep 2008 – Jun 2010

• Concentrations in Strategic Management and Finance

• GMAT: 730 (97th percentile)

• Member of Management Consulting Group, Corporate Management & Strategy Group and High-Tech Group

• Selected member of Business Solutions Group; Devising turnaround strategy for local community center

THE OHIO STATE UNIVERSITY Columbus, OH

Master of Science, Electrical and Computer Engineering Sep 1999 – Jun 2001

• GPA: 3.97; Recipient of merit based University Fellowship at the Ohio State University

ANNA UNIVERSITY Chennai, India

Bachelor of Engineering, Electrical and Electronics Engineering Aug 1995 – Jun 1999

• GPA: 3.92; Recipient of University Gold Medal for graduating at the top of Electrical & Electronics Engineering class

• Recipient of Golden Jubilee Alumni Award for all round excellence in academic & extra-curricular activities chosen

from a class of 1150 students

EXPERIENCE

INTEL CORPORATION San Jose, CA

Design Methodology Lead Mar 2006 – Aug 2008

• Provided technical leadership to division’s senior management in setting project directions and goals for Intel’s next

generation tera-scale graphics processor

• Led an eight member team in supporting over 300 engineers and improving overall customer satisfaction by 40%

• Collaborated with the design, development and test teams to accelerate product development resulting in project

completion four weeks ahead of schedule

• Analyzed trends in design tools affecting a key chip component. Secured buy-in from management and developed a

solution that saved an average of $1M in tool license costs

Senior Component Design Engineer, Mar 2003 – Feb 2006

• Managed the efforts of a six member team in deployment of a new tool used across four microprocessor projects. The

tool saved 1,000+ work hours per project

• Achieved 25% improvement in team productivity by spearheading an initiative to streamline testing methodology and

upgrade development & testing infrastructures

• Devised an error detection strategy in the design phase of a chip that reduced manufacturing costs by 20%

• Actively involved in recruiting activities and mentored five new hires, integrating them into the Intel culture

• Received three Divisional Awards for excellence in developing design automation tools

Component Design Engineer Aug 2001 – Feb 2003

• Developed innovative methodology that resulted in improved accuracy and 50% reduction in chip design time

• Delivered several project training classes to 50+ engineers & received two project awards for training peers

VIBHA San Jose, CA

Vibha is a non-profit organization, helping underprivileged children in India and the US Jan 2003 – Aug 2008

California Coordinator for Tsunami Relief Efforts

• Instrumental in raising over $74,000 for immediate, short-term and long-term relief programs

• Primary contact and liaison with Vibha (India) for Information & relief update

Race Director for Vibha Run/Walk

• Directed and Coordinated logistics for the 5K and 10K trail race held at Shoreline Mountain View, California

• Managed a team of 80 volunteers in an event that attracted 500 runners & raised over $30,000 in net revenue

ADDITIONAL

• Avid Cricket & Tennis player; Captained Varsity cricket & an amateur team in the Bay Area cricket league

• College football enthusiast; Die-hard Buckeye fan

• Elected VP-Public Relations of the San Jose North Valley Toastmasters club

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