Engineer Design

ARTURO GARCIA ROIZ

SR ELECTRICAL ENGINEER

440-***-**** (home)

*** ******** ** ******

440-***-**** (mobile)

Aurora,OH 44202

roicoffe@ gmail.com www.linkedin.com/in/aroiz

Professional Electrical Design engineer with 10 years experience in RF/Analog design, microcontroller digital

interface and manufacturing test for telecommunications, automotive and semiconductor industries. Full life-

cycle product planning, this include product specification, integration, implementation, documentation and

support.

Skills Summary:

DC Analog: Lowpower, lownoise design (passive/active). Experience with lowlevel signal design (uV) and current

leakage down to 1fA. Signal integrity (high speed clocks/serial communications, ADC/DAC, Instr.Amps)

Digital : 8 bits microcontroller interface/design (HC11, 8051, PIC). FPGA Xilinx Spartan3. Multilayer PCB design.

RF design : Narrowband Receiver (HFSS, Single Band) and Transmitter design (FCC 15.231.247). PA classes A and C (10W).

discrete design to 6GHZ (filters distributed/lumped, signal integrity, matching impedances), Antenna design

and optimization. Currently working on DSSS receivers (FCC 90,95). Composite board dielectric PCB design.

RF Mod : ASK/OOK/FSK/QAM/PSK/Bluetooth

Software : Eagleware, ADS, AWR Microwave Office, Pspice/LTspice, Orcad/Eagle PCB, VB6, C, LabView, Assembler.

Hardware : Scopes, Spectrum/Impedance analyzers, FFT/Noise Figures meters, Logic Analyzer, Vector signal analyzer.

KEITHLEY Instruments 2006-2009

SENIOR RF HARDWARE DESIGN ENGINEER

Member of the R&D department. Assigned to design the next generation of "Semiconductor Parametric

Testers". This new unique tester technology combines for the first time the low current (1 fAmp) and high

frequency measurement capabilities (DC-6GHz). This is a high precision tester used to characterize the

silicon wafer, providing technical data such V-I curves, leakage level (>1fA), bandwidth, transition frequency,

stress breakdown, charges mobility, etc.

Support and continuous interaction with marketing directors, mechanical and software engineers.

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Responsible for project leadership, provide technical supervision and mentoring to test and manufacturing engs.

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Designed the lowleakage/highly isolated motherboard pathways for circuits optimum performance down to the 1fA

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and uV noise. This helped the company to develop and introduce new product capabilities and reduced costs"

Guarding and Interface for lownoise ADCs, high speed digital differential communications –impedance match--.

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RF Multi-path designs that requires to be compensated for Signal reflections due to impedance variations

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through frequency, high vswr, self resonant board parasitics, overall path length, non ideal DUTs.

Modeling/Design of matching circuits, smith charts, RF Simulation Tools, AWR microwave office,

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different calibration techniques applied to wafers (LRL,LRM,SOLT), Network analyzers..

Simulations of back planes on high speed/edge multi pathway configurations.

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High density PCB layout design, products designed were 16-20 layers. Successfullyoriented PCB Cad engineers

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to design these complicated boards. "This helped the company by reducing time to market and board turns"

DELPHI Automotive Systems 2001-2006

RF HARDWARE DESIGN ENGINEER

Member of Delphi's product design team. Responsible for the conceptual development, analysis, testing and

implementation of body controller modules (Bcms) with integrated wireless circuitry. Wireless products lines:

RKE (remote keyless entry) and TPMS (tire pressure monitor systems) working at 315,434MHz for the USA and

Europe markets. Experimental designs at 868MHZ.

Research newconcepts/technologies that help to improve the receiver's performance due to antenna design limitations

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while meeting customer range requirements. The overall activities belowhelped the company to obtain a newhigh

quality products while "meeting the project milestones and project's target/budget"

Overall digital motherboard design, dc-dc power supply, electromechanical interface, fuse strategy planning.

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Re-design newfilter topologies that minimizes the noise overall impact in idle current consumption.

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Thermal/Worst Case Product Analysis development for 10 years life product assurance to meet customer

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specifications; test plans development for product validation and manufacturing testing.

Design of high sensitivity circuits: single ended and differential (balanced)

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Design with super heterodyne and regenerative receivers. Lowpower transmitter systems design.

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Analog Active filter (op-amps) and passive filter design for the base-band signal integrity and phase recovery.

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Discrete and power supply analysis for PSRR and lownoise.

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E xtensive use of high frequency simulators Eagleware Genesys, some exposure to ADS.

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Designs to meet EMC/EMI emissions tests to meet customer requirements.

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Antenna Design (monopoles, helical, patch, loops) and Optimization/Loading effects (antenna tuning,

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matching impedance, resonance, gain, radiation resistance and noise)

Design trade off analysis between IP1, IP3, IP2, NF and dynamic range.

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ADC Telecommunications 1999-2001

RF HARDWARE DESIGN ENGINEER

Development of high frequency passive broadcasting products such as splitters, combiners, equalizers,

directional and bi-directional couplers; used in satellite cable signal distribution companies.

Design and creation newline of RF passive broadcasting products (from DC - 2.15 GHz)

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Construction of RF PCB layouts using micro-strip and coplanar methods with different board dielectrics.

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E xtensive modeling activities for product reliability: software simulators : Eagleware, Smith charts characterization and

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Orcad PCB design.

Introduction and newprototypes transfers.

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Design of automation test equipment that include a diverse kinds of electrical interfaces with MCUs/Discrete analog.

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Software Test GUI with: Lab View, VisualBasic, C, Assembler. Design of Access databases for product statistical and

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yield control.

AWARDS:

USA patent 200******** "Simultaneously ask/fsk demodulation technique".

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Recognition award: Started the RF lab at Delphi and provided training and lead for junior engineers

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EDUCATION / TRAINNING

Institute of TechnologyChih., Mexico June 1998

• BS Electronic Engineer,

New Mexico State University, Las Cruces,NM May 2003

• MS VLSI,

(MS VLSI not completed, workingon thesis report)

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