Engineer Software
Resume:
Ajit Agarwal
**************@*****.***
Summary:
I have about 10+ years of work experience in the area of optimizing compiler technologies, System
Tools,Developer Tools performance Analysis tool (Static Analysis and Dynamic Analysis at run time), EDA
Software Development and system software like Linux Kernel filesystem enhancements . I am passionate in
undertaking technically challenging roles and exploring new technology areas.
Core Competencies
Software developer proficient in using C, C++ in UNIX,LINUX and Windows environment.
Static Analysis and Dynamic Analysis(run time)
Optimizing compilers
In depth knowledge of Compilers, Linkers, UNIX internals.
Linux Kernel Enhancement version (2.6.26.6)
TCL Compiler
GNU Tool Chain.
Expertise in porting the gcc compiler for new Architectures
Migrating to Linux and GNU Tool Chain
Experience in writing compilers for DSP/SIMD architectures.
Instrumenting Oracle Binaries.
EDA Tools Development.
High Level Synthesis.
System Tools Development.
Experience in implementing Code Generation phase and Machine Dependent Optimizations like Instruction
Scheduling and Pipelining phases of a compiler and Register Allocation.
Good knowledge in Object Code Insertion and Profiler Technology (OCI).
Knowledge of different architectures like PA-RISC, Data Flow Architectures.
Experience in assembly language of PA-RISC, IXS-1000,Motorola 68000.
Exposure to Software Engineering Processes like Rational Unified Process (RUP) and Intel’s PLC model. DO-
178B.
Technical Proficiencies:
Platforms Worked on: System V,Linux, Fedora6,Win95, Pentium, WinNT Pentium, Linux 2.0.0, Sun4c sparc
SUNW, ultra-1, Sunos 5.5.1 HPUX 11.x/10.x, PA RISC 1.1/2.0,Real Time operating system, Tru64 Unix.
Software/Language Known: C,C++
Tools : Clearcase,lex and yacc,UML Modelling tool Rational Rose, Cadence Tools Verifault Fault
Simulation,Purify,quantify,purecoverage.
Hardware Description Language : Verilog
Logic Design and Fault Simulation.
Area of competence
Compilers(Code Generation, Low and High Level Optimiztion),Static Analysis,control and data flow
Analysis,Dynamic compiler,Memory Optimization,Development tools, System Tools,Linux Kernel,VLSI
Design Tools,Architecture,Object Code Insertion, Object Oriented Design,Algorithm,Migration tools.
Professional Experience:
Tandel Systems Inc(till date).
Senior Software Engineer
I have been working as a senior software Engineer and involves in following projects for Honeywell Space
Station.
June 2007-June 2008
Migration of software support for Space Station for Honeywell from proprietary compiler to gcc compiler
for Motorola 68000 and migrating from Unix System V to Linux.
July 2008 – Nov 2008
I worked on modification of TCL compiler for new Language features (tcl commands) in Linux. New TCL
Language feature(commands) are decided by Honeywell and I incorporated new TCL Language in
TCL Compiler. Language features exercise Power supply and memory for embedded system.
Different memory utilities are interfaces with TCL Compiler us. Implementation of TCL Compiler
are done in C and Assembly.
I have worked on terminal Emulator in Linux of Honeywell. Data are displayed in formatted sent by test
machine with UNIX system V running software that sends menu items, booting information when the
keystroke is pressed Command and debug feature where we can enter TCL commands and sent to test
machine and we get the data related to command and display the data. Unix commands are also
supported. Also incorporated to run different modules on test machine from linux machine. Used
different library like ncurses in linux and terminal emulator application is multithreaded.
I worked on other utilities of Honeywell. In the utilities the binary files is send from System V and
converted to appropriate format in Linux. In the other utilities binary files are transferred from Linux
to test machine with System V and that get processed in test machine with receiving software. Worked
on interface of Linux and System V.
Environment:
C,C++,Linux,Kernel 2.6.26.6,Unix System V,bash script,,ncurses libraries, pthreads,SVN,CVS.
Nov 2008-till date
Implemented the system V file system in Linux. The test machine of Honeywell is subset of System V and
customized operating system Implementing the same file system in Linux. Also implemented the mkfs and
mount,file size optimization in Linux. This enhancement is done in Linux kernel 2.6.26.6.
Mirafra Technologies Jan 2006 to Jan 2007
Lead R & D Engineer
I have been working as a lead in EDA software Development team. Verilog designs gets transformed to parse
tree and populated to a object model. Various utilities are written on object model that creates module instance
graph. Object model is transformed to signal objects..
Responsibilities:
My work involves design and implementing object model and populating object model from parse tree
Involved in transforming to signal objects.
I have also involved in developing API's on top of Interra's API.Interra API's form the frontend for verilog and
system verilog.
Environment
Linux, C++, g++, Verilog,System Verilog, logic design.
Centillium India Pvt Ltd. May 2005 to Jan 2006
Senior Design Engineer
I worked as a part of DSP Tools team on compiler for sigma processor. Sigma is VLIW like Architecture to
achieve higher instruction Level parallelism. The vector mode enables four Multiply –accumulate (MAC) per
cycle, 300 MHz clock speed with relative low power consumption. My work involves in developing a compiler
for sigma processor. The frontend is taken from gnu Gcc sources and backend is written.
Responsibilities
My responsibilities include extracting the frontend from gnu gcc sources and writing a backend. The backend
work involves Code generation. Register Allocation. Instruction scheduler, Machine Dependent optimization
Environment
Linux, gcc, g++
Hewlett Packard Feb 2003 to May 2005
Associate Software Analyst
Compiler and tools group
O worked as a part of HP performance Analysis tool and binary translation team for IA-64. HP Caliper is an
architecture for software developer tools that deals with executable (binary programs). It allows a framework
that allows building of wide variety of tools for doing performance analysis, profiling, coverage analysis,
correctness checking. Binary translation transparently emulates a 32 bit and 64 bit PA-RISC HPUX
Application on Itanium based HPUX Machine.
Responsibilities
My work involves in dynamic instrumentation technology which allows program instruction to be changed on
the fly with instrumentation probes.
Involved in improving run time performance and adding new features to the product like code inlining, dwarf
information sharing, and virtual table instrumentation.
Worked on superblock scheduler (trace scheduling), loop unrolling and loop invariant code motion for a
dynamic binary emulator which transparently emulates 32 bit and 64 bit PA-RISC HPUX application on
Itanium based HPUX Machine.
Environment
Clearcase, Rational DDTS, C++, C, python, Internal Regression test suite
INTEL November 2001 to Feb 2003
Senior Software Engineer
Compiler Group, Edge Access Division
I worked as a part of Intel Compiler Team, involved in developing a compiler for the Intel’s Digital Signal
Processor, IXS-1000. The processor is based on SIMD architecture having both a vector and a super scalar unit.
The processor with its a multiple delay slots and having a non-orthogonal and restricted VLIW Instruction Set
makes writing a compiler a for it a very challenging and interesting.
Responsibilities:
My responsibilities include Code Generation, Vectorization, Machine Dependent Optimization, and Register
Allocation.
Environment
Win95 Pentium, WinNT Pentium, VC++,C++.
Rational Software Corporation(Now IBM) April 2000-November 2001
Developer Tools Group
Rational Purify/Quantify/Pure Coverage are a complete set of automated runtime analysis tools for improving
application performance and quality. These tools use Object Code Insertion (OCI) Technology, to insert
memory-checking, profiling and monitoring instructions into the object files, shared libraries and executables.
Responsibilities
Worked on maintaining and enhancing Rational product called purify, quantify and pure coverage.
Work involves enhancing purify/quantify for MXN thread,MX1 and 1X1 kernel threads, different new linker
features and instrumenting Shared library. I understood the products completely in short span and
enhancing the above features.
Wrapping of system call API to do parameter checking for memory leaks and does mixed case instrumentation.
I was involved in instrumenting Oracle database application like instrumenting the oracle libraries and
instrumenting the database application.
I was involved in design, coding and testing of these features.
I was also involved in defect fixing of different problems that deals with different compiler features and control
and data flow analysis.The work involves dealing with different object file format like SOM and ELF and
low level features.
Different Architectures concepts are incorporated like delay slot code optimization etc.Implemented new and
efficient locking technique that speed up the performance of the product.
Environment
Clearcase, Rational DDTS, C++, C, Internal Regression testsuite, Perl
Silicon Automation Systems Ltd July 1998 - March 2000
(Electronic Design Automation)
India.
In silicon systems I worked in the area of compilers and Electronic Design Tools (EDA) and Arcitecture.
Responsibilities
I was involved in the design of tools using object oriented Concept (OOAD) with C++ and coding with Ellmtell
Standard in VC++ environment.
I was also involved in the design of intermediate data structures.
Projects completed while on assignment with Sillicon Automation Systems Ltd.
Sharp Corporation Ltd (Japan) Aug 1998 - November 1998
Role: Team Member
SAS was developing a comprehensive tool chain for Data Flow Processor. Toolchain involves Flow Graph
Editor, optimizer, allocators, Estimator and DDMP Simulator, synthesis tools. Flow Graph Editor which
captures the Data Flow program and converts to Assembly code for that processor which is taken as input by
simulator
Responsibilities
My Role was in developing the tool that takes Data Flow program captured through Data Flow program and
converts into Assembly code. Assembly is given to assembler developed by Sharp to generate the object
code.
Later I was involved in Estimators and allocators.
Environment
Win95 Pentium, WinNT Pentium, VC++,C++,lex and yacc, Visual SourceSafe, STL
Sharp Corporation Ltd December 1998 to Feb 1999
Role: Team Member
Responsibilities
Work involves developing API's using Sockets for communicating two different simulators called ARM and
DDMP Simulator. Packets are generated by ARM simulator and gets stored in buffer. When DDMP
simulator needs any data it calls socket API to fetch the data buffer stored by ARM Simulator.
BSD Berkely sockets are used for communicating between two simulators.
Sharp Corporation Ltd March 1999 to Jan 2000
Role: Team Member
Responsibilites
The work involves developing High Level Estimators tools for estimating different parameters like Memory
Latency, CST Memory, Program storage Memory, FC Memory Bandwidth. These parameters are very
specific to data flow Asynchronous processors. All data flow programs related DSP and Image processing
which has inherent parallelism are tested for the tools developed by us.
I was also involved in developing a tool for automatically mapping data flow programs on Data Driven Media
processors. The mapping process should balance the dynamic load among the processing elements while
satisfying different constraints.
My Roles coauthored Requirement Specification, High level Design using object oriented approach, coding
testing.
Environment
Win95 Pentium, WinNT Pentium, VC++, C++,lex and yacc, Visual SourceSafe, STL,UML.
M.S Projects:
Completed Six Months project at cadence Design Systems (I) Private LTD (R&D Center Noida)
I was involved in development of utility for a cadence tool called Verifault-XL. The utility is VfAdvisor that
parses the design and report about different option settings.
Simulation of Distributed Mutual Exclusion Algorithm,Distributed Deadlock Algorithm
Image Compression and Pattern Restoration using Neural Network.
Persistent Data Structure using OOP methodology.
Genetic Annaeling Algorithm for Optimization problem.
BS Projects:
Simulation of Multiprocessor System
Construction of pascal compiler, PDP-11 Assember and simulator and text editor
Education Qualifications:
MS (Computer Science) BITS Pilani Rajasthan with distinction (9.2 CGPA /10)
BS (Computer Science): Graduated Manipal Institute of Technology Manipal with distinction (70% marks)
References: Available on request
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