MATTHEW SLADICKA
480-***-**** ********@*****.***
PROFESSIONAL SUMMARY
A ten year Senior Engineer with proven track record of technical experience ranging from sustaining,
technical support, new product development, and quality improvement. A certified six sigma black
belt highly experienced in project management, development and continuous improvement methods.
A Strong problem solver with ability to adapt to change and new challenges. Areas of expertise
includes:
PROFESSIONAL EXPERIENCE
ASQ SIX SIGMA BLACK BELT CERTIFICATION: Freescale Semiconductor Project work
• Led a team using Six Sigma DMAIC methodology in making a major front end process change
that reduced output parameter variation by 85%, reduced defectivity failures by 40%, increased
yield by 2%, and reduced process time by 30%. Project results had an estimated annual saving
of $79,000/year not including the yield gain. Received Freescale Technical Excellence Award for
the Most Significant Technical Contribution in Q3 2004.
• Managed a cross functional team in utilizing DMAIC methodology to isolate and eliminate an
overlay defect that was masking out critical killer defects at an inline inspection point.
• Demonstrated DOE methodologies through performing a half fraction 5 factor 2 level screening
experiment on flat films monitoring four output variables that led to a 30% reduction in variation
for output variables.
• Maintained Statistic Process Control and FMEAs for Oxide and Poly Etch processes.
• Demonstrated Multi-vari Analysis (MVA) statistical techniques by identifying sources of variation
for a critical output parameter.
FREESCALE SEMICONDUCTOR (FORMERLY MOTOROLA), Chandler, Arizona 1998 – 2009
Yield Enhancement Module Engineer 2006 – 2009
Maintained baseline defectivity levels for the gate module by implementing SPC controlled on-
product KLA monitors to detect defect excursions. Reduced baseline defectivity levels by managing
cross-functional continuous improvement teams. Set defectivity testing requirements for all
Corrective Action Board engineering changes that occur in the gate process module.
• Isolated root cause for defect excursions, applied containment, dispositioned non-conforming
product in a Material Review Board, and worked with responsible process engineering
department to identify short term and long term actions to prevent repeat occurrences.
• Identified continuous improvement projects and managed cross functional teams to lower
baseline defectivity. Some projects reduced defectivity at an inspection point by as much as
50% and increased baseline yield by more than 5%.
• Reviewed Failure Analysis Reports to assist Quality department in isolating root cause for
product returns so preventative actions could be implemented.
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• Trained Yield Enhancement Team on new software which contains CAD renderings of Photo
Reticles. Use of software helped identify several design mistakes which was attributed to as
much as 15% yield loss.
Senior Process Engineer 2001 – 2006
Sustained etch equipment in a manufacturing environment through utilization of SPC methods to
control and improve etch processes. Worked with device engineering and yield enhancement to
improve the Poly etch and Front End Oxide (FOX) etch processes to achieve industry benchmark
yields. Optimized etch tool and process performance for reduced variation, improved process
capability and improved product yield.
• Qualified new AMAT DPS poly etch chambers and released into production by ensuring that
outputs met Purchase Agreement requirements and had no adverse effect on parametric or
yield. Implemented a new equipment modification which increased throughput by 20%.
• Developed a methodology for monitoring and controlling etch tool defectivity performance by
using an on-product defectivity monitor resulting in a savings greater than $100K/year. The
method resulted in quick root cause identification for tool and integration defectivity issues and
was later propagated across all Process Engineering Departments.
• Qualified a modified capture ring on DPS Poly Chambers which eliminated backside helium faults
and had a savings of $250K/year due to inline scrap reduction.
• Utilizing DMAIC Methodology identified interactions between different FOX etch processes and
separated them to eliminate process interaction variation in process output parameters.
• Utilized and created Failure Detection Control Models to detect tool performance deviations and
automatically shut equipment down as the deviation happens.
• Created, maintained, and documented changes in all Poly and FOX etch specifications.
• Mentored new engineers and process technicians in troubleshooting, risk assessment, SPC and
process dynamics.
Process Integration Engineer 1998 – 2001
Responsible for development of characterized etch processes to be transferred into manufacturing
factories. Required to design experiments, analyze data, solve problems, oversee daily process
performance and ensure successful transfer.
• Developed MIM Oxide Etch Process using a Screening Experiment and a Robust Design
Experiment optimizing four separate output parameters to meet design requirements.
• Completed development, characterization and transfer of 0.35 micron HBT CMOS process, MIM
Process, and 0.5 micron BiCMOS etch process to a manufacturing factory.
• Developed processes, procured equipment, and oversaw conversion of eight inch Si equipment
for six inch GaAs production.
• Designed an interfab communication tool making use of the Motorola’s intranet, Core directory
and Oracle database that got propagated to all Motorola Semiconductor Factories Worldwide.
• Installed Gasonics L3510 and a LAM4420 and through testing confirmed that the tool
performance fulfilled the purchase agreement requirements before releasing to manufacturing.
• Mentored intern on a broad range of semiconductor projects resulting in her accepting a full time
process engineering position.
EDUCATION
Bachelor of Science, Chemical Engineering
North Carolina State University, Raleigh, North Carolina
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PROFESSIONAL DEVELOPMENT