919-***-****

****, ******** *****,

Pranav Hangalur abnohr@r.postjobfree.com

Raleigh NC 27606

Objective: Being passionate to excel, I wish to be a part of a team working on challenging projects (Full time position)

Education:

Master of Science (M.S) in Electrical Engineering GPA 3.63 (current). Expected May 2009

North Carolina State University, Raleigh, NC

Bachelor of Engineering (B.E) in Electronics and Communications, (First Class with Distinction, May 05)

Visvesvaraya Technological University, SJ College of Engineering, Mysore, India

Technical Skills:

VLSI design/Process simulation tools: Cadence (Virtuoso), Synopsys (HSPICE, TCAD), Mentor Graphics (Calibre),

Silvaco TCAD (supreme, atlas).

Programming language/tools: MATLAB, Mathematica, C/C++ (STL), GCC, GDB, Clearcase, Purify, Wireshark,

Xcode (Carbon), POSIX thread library.

Operating systems: HP UX, Linux, Solaris, Mac OS X, Windows 2K, XP, Vista.

Graduate Courses: VLSI Systems Design, Digital Electronics, IC Tech. & Fabrication (Theory & Lab), Physical

Electronics, Semiconductor thin film technology, Principles of MOS Transistors, Fundamentals of Power

Electronics, Frontiers of Nanoelectronics, Advanced Mathematics for Engineers and Scientists

Academic Projects/ studies (nanoelectronics/VLSI design):

Semiconductor Process design: Designed a 65nm semiconductor process with appropriate doping/thermal

processes, simulated devices (MOSFETs, Diodes and Capacitors), designed the layout of test circuits.

Device Modeling: Involved in the modeling of ~22nm MOS transistors (Si & Ge devices both PMOS & NMOS

using Synopsys TCAD) suggested as the target for 2008 09 in the ITRS roadmap.

Fabrication and Test: Fabricated and characterized MOSFETs, capacitors and test devices on a 4” wafer using

3µm technology at NCSU nanofabrication facility.

SRAM design: Involved in the design and layout of 128kbit SRAM for 45nm technology using the NCSU

freePDK library.

Modified SAFF design: Designed a modified Sense amplifier flip flop using the 45nm technology. Non ideal

input sources used – optimized to reduce power consumption.

Transceiver design: Designed a 1 bit wide transceiver designed to operate at 90 C with non ideal input sources

with stringent eye opening requirements – optimized to reduce power consumption.

Boost converter design: Designed a boost converter with voltage feedback control loop. Designed a PID

controller for the project

Physics based IGBT model: Studied the physics based device models of IGBT for circuit simulation, including

the popular Hefner’s model of Si IGBT with an aim to develop a model of SiC IGBT.

Work Experience:

Software Engineer, Hughes Software Systems, Bangalore (known as Flextronics soft. Systems, now as Aricent)

(Aug 05 Mar 07): Involved in the design, development and testing of MSC simulator (Mobile switching centre) – a

multi threaded process written in C++, as part of a 3G simulator package.

Involved in the design, development and testing of a multi threaded process monitor application used to control and

monitor processes, part of 3G simulator. Worked with linux kernel APIs

Intern, Hughes Software Systems, Bangalore (Feb 05 to Apr 05): Developed an SNMP Manager

References: Provided upon request.

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