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Engineer Design

Location:
6106
Posted:
March 09, 2010

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Resume:

Aaron Pathripala

*****.**********@*****.***

718-***-****

*** **** ******, *** ***

Hartford, CT – 06106

OBJECTIVE

To obtain the available “Hardware Engineer” position that utilizes my knowledge in Electrical and Computer Engineering.

EDUCATIO

Polytechnic Institute of ew York University, Brooklyn, NY-11201

Master of Science in Computer Engineering and Graduate Certificate in Wireless Communication, Jan 2009 – CGPA = 3.37

H.M.I.T.S., Jawaharlal ehru Technological University, Hyderabad, India

Bachelor of Technology in Electronics and Communication Engineering, May 2006 – GPA = 3.6 (72%)

SKILLS

Languages: Assembly, C, SQL.

Hardware: VHDL.

Databases: MS Access.

CAD / EDA Software: pSpice, Multisim, Modelsim, Xilinx, Cadence Virtuoso.

Operating Systems: MS Windows 95/98/NT/2000/XP/Vista, UNIX.

Processors Knowledge: 8086/85, Computer Architecture (MIPS, VMIPS), Advance Pipelining, Parallel Processing.

Reporting Tools: Business Objects 5.1, Crystal Reports 2008, Dashboards, MS Excel

Other Tools: MS office Suite, Adobe.

PROJECTS

INTEL WISP UHF RFID (860 MHz – 960 MHz)

•Research project on WISP (Wireless Identification and Sensing Platform) UHF RFID to establish a secure and efficient

communication between the interrogator and the tag.

•Documented on most of the available published papers focusing on communication protocol using Intel WISP.

STATIC CMOS CIRCUITS

•Designed the Schematics along with the layouts of all the basic CMOS circuits using static CMOS Technology in Cadence Virtuoso.

RUN LENGTH ENCODER

•Designed the schematics along with the Layouts by checking the DRC, LVS results and Simulated them using Analog Environment

tool in Cadence Virtuoso on UNIX (Solaris) platform.

•Designed the schematics of 8-bit Carry-Look-Ahead adder along with its layout and simulated in Cadence Virtuoso.

RC5 MODULE

•Implemented 64-bit Encryption & Decryption of RC5 algorithm on the FPGA (Xilinx Spartan 3 starter kit) using VHDL & Xilinx.

16-BIT MICROPROCESSOR

•VHDL coding for a 16-bit microprocessor to perform the basic arithmetic operations.

RESILIENT PACKET RING (RPR)

•Research on the fundamental concept of RPR and its functionality.

•Its traffic priority and Fairness algorithm used and the performance of RPR as a whole.

DESIGN AND TESTING OF 90º TAPERED-STRIPLINE DIRECTIONAL COUPLERS

•Design and testing of 3db 90 degree hybrid dual directional coupler, centered at 2GHz by using coupled striplines at Flic Microwaves

Pvt. Ltd.

RELEVE T COURSES

Advanced Computer Hardware Design (VHDL) VLSI Design

Principles of Communication Theory Computer Architecture

Electronic Devices and Circuits Principles of Digital Communications “Mod & Cod”

Wireless Personal Communication Systems Wireless Communication. - Channel Mod & Impairing Mitigation

EXPERIE CE

Polytechnic Institute of YU (Assessment & IR), 6 Metrotech Center, Brooklyn NY - 11201 02/07 - 01/09

Graduate Assistant

•Generate the institutional common dataset and statistical reports that is uploaded on Assessment & IR website.

•Generate reports that are used to report to USnews.com, ABET, IPEDS, NSSE and other State and Federal reporting sites that were

critical for accreditation of the University.

•Generate reports that are used for institutional assessment.

•Maintain the historical Degree and Enrollment Database.

•Extensive use of pivot tables and generation of complex reports and charts.

•Retrieving Data using complex joins in MS Access database.

•Conduct alumni surveys during the years 2007 and 2008.

•Created complex dashboards using MS Excel which enhanced decision making

Environment – MS Access, MS Excel, Pivot Tables, SQL Queries, Join Tables, Retrieve tables

HO ORS

Distinction in Bachelor’s Degree.

Polytechnic Institute of NYU Graduate Center Scholarship.

ACTIVITIES

Student member of IEEE and IEEE Computer Society.

Member of Graduate International Students Association (GISA), Polytechnic Institute of NYU.

Organized educational tours for the ECE department in February 2005 and 2006.

Represented my school and college in various sports and events and was the captain for the school cricket team.

STRE GTHS

Fast learner, detail oriented, commitment to work coupled with team spirit and good leadership qualities.

Multitasking, flexible and good time management skills

AVAILABILITY

Immediate

SALARY REQUIREME T

Open



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