Engineer Project Manager

Ren D. Earl

***** *. ***** ****

Oregon City, Oregon 97045

Phone 208-***-**** E-Mail *******@***.***

OBJECTIVE

To use my experience, mechanical aptitude and education in the semiconductor industry as a

Process Enhancement engineer or Failure Analysis specialist.

EXPERIENCE

Senior Engineer - Yield Enhancement & Failure Analysis, Magna Chip Semiconductor 2007 - 2008

• Developed data capture, analyzation and distribution infrastructure to facilitate design and process decisions

between distant divisions.

• Coordinated production initial test routines with final test yield models to eliminate customer returns.

• Generated predictive probe test parameters to efficiently predict the effects design changes on test vehicles.

Senior Engineer - Yield Enhancement & Failure Analysis, Micron Technology 2002 - 2007

• Evaluated data generated from process, mechanical, or procedural changes made to the product line from all

areas of the production sequence.

• Published concise reports on data from all processing areas with recommendations for further actions if

necessary for implementation.

• Possess broad knowledge base to understand the process change made by Design or Process to derive electrical

or physical tests needed to accurately measure the impact of any expected and unexpected changes.

• Characterized process or design changes utilizing Probe, Param, Inline, and Test data sets.

• Use of DOE for planned lot splits to optimize process and enhance yield. OTC software programs used were

JMP, Origin and Cornerstone to generate the most efficient models for best resource utilization.

• Correlated data from Probe, Test and Inline to Simulations which produced forward looking performance

estimates.

• Directed optimization efforts for single and double sided containers using alumina-hafnia and alumina-zirconia

dielectrics.

• Implemented leakage improvements in capacitor electrodes form evaluation of Probe and Inline metrics.

Senior Engineer - Advanced Transistor Development, Micron Technology 1999 - 2002

• Project manager of advanced transistor development projects in a highly matrixed responsibility environment.

• Developed advanced vertically integrated access transistors to reduce production cost yet provide scalable

solutions for increased performance requirements.

• Achieved fully self aligned capacitor over bit line process flow that reduced the mask count and required

number of critical dimension Photo-Etch steps while enabling low selectivity spacer etches that still kept line-

space tolerances within prescribed limits.

• Designed several novel gate oxide and gate performance test structures for use with advanced transistors.

• Created a global coordinate system for process uniformity and experimentation facility.

• Produced procedure for identification and elimination of repetitive defect.

Embedded DRAM Senior Parametric Engineer, Micron Technology 1997 - 1999

• Multi Chip single packaging effort containing SRAM, DRAM, and Processor.

• Developed flow to optimize merging of existing CMOS and BI-CMOS processes.

• Characterized performance data to combine like processes and reduce undesirable effects caused by subsequent

fabrication steps.

• Developed higher temperature contact salicide process.

• Provided test and measurement continuity between multiple participants.

• Compiled, correlated, tracked, and published performance against end user requirements.

Ren D. Earl Page 2

Phone 208-***-****

E-Mail *******@***.***

Lead Production Parametric Engineer, Micron Technology 1994 - 1997

• Evaluated, diagnosed, and predicted what effects would transpire on yield and device performance from subtle

changes made to tools and process steps from intended improvements and unintentional modifications.

• Troubleshoot Probe and Test results that shifted SPC control points and determined link to Fab steps where tests

were enacted to eradicate undesirable defects and increase process uniformity.

• Developed a standardized conversion documentation process that allowed real time feedback to process owners

and managers that displayed the current results and stage of completion.

Lead Diffusion Engineer, Micron Technology 1989 - 1994

• Shift lead in diffusion responsible for seven engineers and four technicians which maintained the mechanical

and process control.

• Provided training, determined priorities, scheduled special work requests, certified production compliance,

ensured safety, and delivered informational updates.

• Involved in projects for adjusting mechanical and process metrics to improve throughput, downtime, and

measurement accuracy.

EDUCATION

Bachelor of Science in Electrical Engineering Technology

DeVry Institute of Technology, Dallas, Texas. 1985 – 1987

GPA – 3.75

SKILLS

• Data analysis using JMP, Excel, Cornerstone and Origin

• Report writing for interoffice communication using Word and Power Point.

• Layout and design rule review using KF2 and Cadence.

• Programming using PERL and Macros.

• Bench measurements using Agilent 4156, LCR, DVM.

PATENTS

• Three patents for GMR bit programming stabilization

• Three patents for single metal line capacitance reduction

• Five patents for self aligned magnetoresitive containment

• Three submitted disclosures for self aligned surface MOS enhanced isolation transistor schemes

• Two submitted disclosures for programmable variable resistance cells

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