Engineer Process
Resume:
Weiming He
Glen Allen, VA 23059
abnn4j@r.postjobfree.com
Professional Profile:
• Ph.D. in Electrical Engineering with extensive knowledge in Solid Physics,
Material Science, surface analysis and material characterization
• More than 6 years experience in semiconductor industry in R&D or manufacturing
environment
• Process engineer experience in semiconductor industry with proven record of
success on technology transfer, process optimization and failure analysis, defect
reduction
• Demonstrated ability of interfacing cross-functional organizations
• Experience in process improvement, project management, problem solving and
data analysis skills
Professional Experience:
Infineon/Qimonda, Sandston, VA 2005-2009
CMP Process Engineer & Metrology Engineer
• Transfer products and processes from R&D to Production
• Developing and optimizing recipes for new & existing products
• Establish procedures and qualification plan for brining new processes on line
• Provide troubleshooting assistance for manufacturing processes
• Perform process characterization to document new and existing processes/products
• Perform capability, repeatability and cost analysis on processes
• Support downstream customers and new product development
• Implement SPC and FDC for process/tool control
• Analyzing and preparing reports of experiments & process/tool releases
• CMP process owner and CMP online metrology (Nova) tool owner
• Cost reduction and productivity improvements using lean six sigma manufacturing
skills
Oregon Graduate Institute, Beaverton, OR, 2002-2004
Research Assistant,
• High-dielectric gate oxide deposition by atomic layer deposition (ALD)
• Hands-on experience on film characterization by Spectroscopy Ellipsometer, AFM,
SEM, XRD, optical microscopy for analysis of thickness, microstructure and
composition.
• Hands-on experience on device electrical characterization, including wafer probe
station, HP/Agilent semiconductor parameter analyzers.
Fujitsu Microelectronics Inc., Gresham, Oregon, 2001-2002
Yield Analysis Engineer
• Instrumentally identified the root cause of problem lots; delivered engineering
resolution to manufacturing group
• Led engineering team and drove optimization of process flows
• Performed parametric troubleshooting on semiconductor devices
• Characterize and identify yield limiting failure mechanisms through data analysis
and fail bit map techniques
• Correlate defects to yield loss and identify baseline defectivity opportunities
• Find root cause for inline excursion and provide solution recommendation
Auburn University, Auburn, AL, 1998-2000
Research Assistant
• Hands-on experience on epitaxial growth and characterization
• Hands-on experience on thin film deposition (oxide and metal deposited by
evaporation and sputtering), plasma/wet etching, rapid thermal annealing,
photolithography
Alphatec Electronics Corporations, Shanghai, China, 1991-1998
IC Packaging Process Engineer
• Qualified new IC packaging equipment and process
• Collected and analyzed data to sustain the process
• Interface with other engineering groups and vendors for quality goal
• Participates in design reviews for product and process compatibility
• Developed process improvement in yield, work flow
• Perform reliability test
Technique Skills:
• Experience in quality management tools (Lean 6 sigma, 8D, FMEA)
• Hand-on experience with AFM, SEM, EDS, crystal x-ray diffraction, SE, optical
microscopy
• Software skills on JMP, SPC, DOE, Knights Yield Analysis, PCA, MatLab,
AutoCAD
• Experience in semiconductor parameter analyzers (capacitance-voltage, Current-
voltage), network analyzer
Education:
• Ph.D., Electrical Engineering, Oregon Graduate Institute, OR, 2004
• M.S., Materials Science, Auburn University, AL, 2000
• B.S., Materials Science, Shanghai JiaoTong University, China, 1991
Publication:
• Weiming He, Steven Schuetz, Raj Solanki, John Belot, and James McAndrew,
“Atomic Layer Deposition of Lanthanum Oxide Films for High-kappa Gate
Dielectrics “, Electrochem. Solid-State Lett. 7, 2004, G131-133
• W. He, R. Solanki, J. F. Conley, Jr., and Y. Ono, “Pulsed deposition of silicate
films”, J. Appl. Phys., Vol 94, No 5, 2003, pp. 3657-3659
Contact this candidate