Engineer Process

Scott W. Bailey

***** ***** ******* ****** *****: 623-***-**** (Cell)

San Diego, CA 92128 E-mail: **********@***.***

Objective A challenging career as a Staff Level Process Engineer

• 1996 BS Materials Science and Engineering, University of Florida

Education • 2003 MBA, Arizona State University

Professional

Illumina, Inc.

2008 – Current San Diego, CA

Experience

Senior Process Development Engineer - Veracode Genotyping Start-Up

• Responsible for transfer and scale-up of Veracode bead processes into high volume

manufacturing

• Responsible for preparing manufacturing line which consisted of chemistry attachment,

oligonucleotide processes and product packaging for FDA approval

• Responsible for developing non-destructive measurement techniques for process control

• Experience with IQ/OQ/PQ validation plans

January 2007 – December 2007 Technical Instruction – Contractor for STMicroelectronics

• Performed technical instruction about semiconductor processing to line engineering

technicians through Phoenix College. (Course was 9 credit hours)

• Achieved our goal in bringing up the level of knowledge at the site so that the technicians

would be able to make more informed decisions

• Course content covered wafer pulling using Czochralski method, through wafer dicing

covering all functional areas such as Diffusion, Ion Implant, CVD, Epitaxy, Etch,

Photolithoghraphy

ST Microelectronics

2000 – June 2006 Phoenix, AZ

• Defect and Wafer Fab Yield Champion (2002-2006)

• Drove Diffusion Wafer Fab Yield from worst to first within 2 years by focusing team on high

impact events and identifying and driving actions to reduce likelihood of those events

• Facilitated cross-functional teams to resolve of multiple yield killing defect e xcursions in

Diffusion -

Aluminum contamination in a pre-gate clean caused by degradation in Tefzel

o

coating of clean vessel

Arcing in HDPCVD tool due to edge antenna created from 60 steps earlier

o

• Supported both Device Engineering and Process Engineering via Data Mining using KLA

Ace XP to determine comple x problem sources and interactions

o This required ability to write software code to format the vast amount of data

o The analysis reduced the time to identify a problem from a few days to a few

hours

• U sed Advanced Process Control Data to correlate defect excursions back to the source tool.

• Supervised the Engineering activities related to Wafer Fab Yield and Defect issues

• Wafer Fab Yield – Tracked team action plans to completion and reported status to Senior Site

Staff.

STMicroelectronics Thin Films Process Engineer

• Optimization and characterization of thin dielectric silicon dioxide (SiO2) layer for DRAM

processes and it’s effects on process integration, threshold voltage and dielectric breakdown

• Sustained all CVD area processes, and worked on tool excursions

• Implemented Turbo On Clean on HDP-CVD, eliminating excursions from the turbo pump

• Project Management: Rolled out new hardware and process across toolsets. Developed

qualification plan and coordinated with quality, equipment engineering, and tool vendor.

• Quarterly Achievement Award – Defect reduction team focusing on back-end defects

• Developed and Industrialized the remote cleaning process for C3 F8 for chamber dry cleans

resulting in two publications, one of which was presented at Semicon West 2002.

• Co-Authored “Advances in Remote Plasma Sources for Cleaning 300 mm and Flat Panel

CVD Systems”, Semiconductor Manufacturing, August 2003.

• Teamwork: worked with fellow engineers in other areas with the Information Systems group

on the design and implementation of chamber tracking for cluster tools. This helped

reduce human error, resulting in seamless management process chamber status.

• Tool Defect characterization – developed methods for identifying sources of particles on tool

qualifications using Semvision (SEM/EDX)

• Maintained and updated all specifications as processes were changed or per ISO9001

White Oak Semiconductor

1997 – 2000 Richmond, VA

CVD Films Process Engineer - Fab Start Up

• Co-authored Patent: Maskless STI planarization. Worked with CMP and device integration

on elimination of large feature mask and plasma etch step. Process was successfully

implemented, which resulted in lower costs and increased die yield.

• Ensured process readiness and successful technology transfer, resulting in high yielding first

run silicon at ~66% and at an industry record 11 months from ground breaking to first

silicon.

• Designed experiments to investigate the process windows of key parameters of the HDP-STI

process using DOE methodology. Fab cluster specifications were derived from the

experiments

• Developed new clean process for the AMAT 5200 PECVD chamber to reduce contamination

and increase productivity by 50%

• Developed new HDP-CVD ILD and STI oxide processes for sub .2µm processes

• Documented all recipes and procedures in specifications.

• Familiar with SEM, TEM, SIMS, VPD, EDS, XRF, XRD analysis techniques and results

• Used SIMS analysis technique to reduce metallic contamination in oxide films

5/96 – 8/96 GE Corporate R & D Intern, Niskayuna, NY

Internship/

• Semiconductor Packaging

o Worked with Staff Engineers on optimizing molding process of advanced multi-level

Assistantship

packages

Identified key variables which caused variation of material and reported results and

o

recommendations

JMP (DOE), ),Statistical Process Control (SPC), Synergy, MS Office, MS Project, Visual Basic

Skills Programming, Semvision, Knights, KLA Ace XP Data Mining, Excel VB Programming

Hobbies/ Golfing, Sailing, Traveling, Softball

Recreation

References Todd Gandy, Director of Process Engineering, STMicroelectronics 602-***-****

Jim Darr, Process Engineering Manager, STMicroelectronics 602-***-****

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