Thirumalesh Bannuru
***** ***** ***** ***, *** **04 E-mail: abnhse@r.postjobfree.com
Maple Grove, MN 55369 Phone: 503-***-****
OBJECTIVE
Experienced Process Integration Engineer looking for an opportunity where he can utilize his current knowledge and
skills in materials science/mechanical engineering and grow in directions aligned with the business goals of the company.
COMPETENCIES
• Semiconductor wafer process flow and assembly/packaging
• Lean Six Sigma problem solving by DMAIC approach
• Materials Characterization and Failure Analysis
• Root cause finding of process excursions in high-volume manufacturing
• Design of Experiments (DOE)
• Data mining and statistical data analysis
• Mechanical design using CAD
ACCOMPLISHMENTS
Driven quality white papers (transition from pilot to full-scale implementation) to completion and propagated
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them across partner factories resulting in cost savings of $10 million+. Member of process/tool change control
board/ management.
• Led inter-disciplinary task force teams to resolve integrated defect/yield (excursion) problems using 8D problem
solving techniques in a leading edge 300 mm microelectronics fabrication facility. Positive impact on factory
operations goals and quality indicators.
• Performed data analysis and made data driven decisions for work groups created to improve ‘Back End Of Line’
(BEOL) process and reduce inline defects.
• Developed software code for routine pilot line data analysis resulting in 50% time savings.
• Facilitated the ‘Copper (Cu) polish task force’ reducing blotchy residue defects by 90% on wafers.
• Successfully completed research oriented fractography studies on Pb-free solder C4 interconnects in flip chip
electronic packages using mechanical shear test leading to significant learnings on crack propagation path.
• Developed novel Au-V2O5 thin films as part of doctoral research leading to journal publications and utility patent.
• Automated data collection and control of instrumentation in laboratory equipment using LabVIEW resulting in
flawless execution of experiments.
• Maintained complex laboratory equipment, developed Standard Operating Procedures (SOP) and trained people
using best known methods.
EXPERIENCE
Process Integration Engineer 12/07 - 09/08
INTEL Corporation, Logic Technology Development, Hillsboro, OR, USA
Owner for integration duties involving thin film and metallization modules in Back End (BE) for microprocessor (1264.5)
and derivative (1265.x) chipset technology.
• Assisted modules in trouble-shooting semiconductor process related problems to sustain a robust 65nm process in
the back end of line (BEOL). Analyzed E-test, sort, inline data.
• Contributed to integrated ‘process window margin’ studies to solve end of line yield fallout.
• Collaborated with individual process modules (PVD, CVD, Etch, CMP polish, Barrier, ECP, Planar) to
understand integrated defect issues in 300mm micro fabrication clean room environment.
• Continuous process improvement using Statistical Process Control (SPC) and lean (kaizen) manufacturing to get
best-in-class die yields.
• Rolled up data in support for pilot line experiments and to monitor any process deviations at CMP and
metallization modules.
Doctoral Intern 06/07 - 09/07
INTEL Corporation, Quality and Reliability, Hillsboro, OR, USA
• Investigated aging phenomenon in Pb-free solders using Cold Ball Pull method as Quick Turn Monitor (QTM)
and correlated to shock tests in order to validate the current Best Known Method (BKM) for drop-shock
reliability tests post-Surface Mount Technology (SMT) process.
• Led a field trip to printed circuit board (PCB) manufacturer called Merix in Hillsboro, OR in order to advance the
Thirumalesh Bannuru
team’s knowledge on PCB fabrication.
Doctoral Research Assistant 01/02 – 05/07
Lehigh University, Bethlehem, PA, USA
• Developed and characterized process for fabrication of Au thin films with VOx nano-dispersions.
• Studied contact material issues for ohmic (contact) RF MEMS switches and suggested solutions to minimize
wear and degradation.
• Determined reliability (mean time to failure) of microswitches to improve life cycle and minimize contact wear.
• Developed and characterized novel low residual stress Pt/Ir-IrO2 thin films for integration with piezoelectric
MEMS applications.
• Designed and implemented data acquisition and control systems (hardware and software; LabVIEW) for thin film
stress measurement by membrane resonance, “substrate curvature” techniques.
Doctoral Intern 08/05 – 02/06
INTEL Corporation, Assembly Technology Development, Chandler, AZ, USA
• Performed shear test to understand the fracture mechanism/strength of individual C4 solder joint for next
generation (Pb-free, 45nm technology node) flip-chip package path finding, FMEA.
• Actively supported DOE to understand the acceptable C4 solder bump height tolerance for assembly.
• Assisted in micro void investigations on 1st level solder interconnects (BGA) using X-ray and SEM imaging.
Contributed to task force formed to root cause the problem and participated in substrate supplier review meetings.
Teaching Assistant 08/03 – 05/04
Lehigh University, Bethlehem, PA, USA
• TA for the courses titled: Structure and Characterization of Materials, Mechanical Behavior of Materials and
Introduction to Solid Mechanics (at SUNY).
• Demonstrated use of XRD, SEM, EDS, TEM and LOM equipment to the students.
Graduate Research Assistant 08/99 – 12/01
State University of New York, Binghamton, NY, USA
• Investigated thermal-mechanical behavior of NiTi fiber actuated aluminum metal matrix composites using
Material Test System (MTS) machine.
• Operated the DSC instrument to monitor phase changes in NiTi shape memory alloy fibers.
• Developed data acquisition and remote (computer) control operation of MTS using LabVIEW.
• Generated 3D solid models and subsequent engineering drawings from conceptual level using CAD.
SKILLS
Computer Skills
JMP 7.0 with working knowledge of Statistics & DOE, Klarity defects review software, SQL, CrystalBall, Origin Pro 7.5,
LabVIEW 8.0, AutoCAD 2005, Vellum Solids, Mathematica v5, MS Visual studio 6.0, C++, MS Office
Technical Skills
Electron Microscopy: SEM, Basic TEM Nanoindentation: Hysitron Triboscope on DI
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small sample stage AFM
Chemical analysis: EDS, RBS, XPS
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Thin film deposition: DC Magnetron Sputtering
Completed summer short courses at “Lehigh •
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system, Evaporator (PVD)
Microscopy School”
“Substrate curvature system” to determine stress
X-Ray Diffraction (XRD) •
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in thin films on substrates.
Focused Ion Beam; FEI Strata DB 235
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Thermal Analysis (DSC)
Materials Test System (MTS) and Instron 5567 load •
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4-point resistivity probe
frame •
Data acquisition and control using PCI & GPIB
Dimension 3000; Large sample stage AFM •
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Thirumalesh Bannuru
EDUCATION
Lehigh University, Bethlehem, PA, USA
Ph.D, Materials Science and Engineering, Jan., 2008
Dissertation: Effects of alloying on the mechanical behavior of noble metal thin films for microelectronic & MEMS
applications.
State University of New York (SUNY), Binghamton, USA
Master of Science (M.S.), Mechanical Engineering, Jan. 2002
Thesis: Thermal-mechanical testing of NiTi shape-memory alloy fiber actuated Al metal matrix composites.
Indian Institute of Technology (IIT) Roorkee, India
Bachelor of Engineering (B.E.), Mechanical Engineering, Nov., 1998
PATENT
• “Thin film Au-VOx alloys for contacting MEMS”, Richard P. Vinci, Thirumalesh Bannuru and Walter L. Brown,
full U.S. utility patent filed (12/052,838), March 2008
PUBLICATIONS
• Thirumalesh Bannuru, W.L. Brown, S. Narksitipan, and R. P. Vinci., “The electrical and mechanical properties
of Au-V and Au-V2O5 thin films”, Applied Physics Letters 103, 083522 (2008)
• Thirumalesh Bannuru, S. Narksitipan, W.L. Brown, and R.P. Vinci: "Effects of V additions on the mechanical
behavior of Au thin films for MEMS contact switches". Proceedings of SPIE Vol. 6463 (2007), p. 646306.
• William D. Armstrong, Thirumalesh Bannuru, “Observed dependencies of the large thermal-compressive
response of a NiTi shape memory alloy fiber aluminum metal matrix composite.”, Proceedings of SPIE – Vol.
5761, pp. 388-394, May 2005
• Wenyue Zhang, Joseph P. Labukas, Svetlana Tatic-Lucic, Lyndon Larson, Thirumalesh Bannuru, Richard P.
Vinci and Gregory S. Ferguson, "Novel Room-Temperature First-Level Packaging Process for Microscale
Devices.", Sensors and Actuators A-Physical, 123-24:646-654, Sept 23 2005
• Richard R. Chromik, Thirumalesh Bannuru and Richard P. Vinci., “Internal oxidation and mechanical properties
of Pt-IrO2 thin films.” Mater. Res. Soc. Symp. Proc., Vol. 795, 2004, P. U 8.13.1-U 8.13.6
• R.P. Vinci, Thirumalesh Bannuru, S. Hyun and W.L.Brown, “Fabrication of Pt-IrOx and Au-V2O5 Thin Films”,
Key Engineering Materials, Vols. 345-346 (2007) pp 735-740
• Wenyue Zhang, Joseph P. Labukas, Svetlana Tatic-Lucic, Lyndon Larson, Thirumalesh Bannuru, and Gregory S.
Ferguson, "Novel Room-Temperature First-Level Packaging Process for Microscale Devices.", EUROSENSORS
XVIII Conf., Rome, Sep. 2004
• Thirumalesh Bannuru and Armstrong W. D., “Observed dependencies of the large thermal-compressive response
of a NiTi shape memory alloy fiber Aluminum metal matrix composite on maximum tensile strain imposed
during a preceding room temperature tensile process.”, Metallurgical and Materials Transactions A, Vol 35A,
April 2004-1403
PRESENTATIONS
• Thirumalesh Bannuru, S. Narksitipan, W.L. Brown, & R.P. Vinci, "Effects of V additions on the mechanical
behavior of Au thin films for MEMS contact switches",Oral presentation at SPIE, Photonics West 07,
Reliability, Packaging Testing & characterization of MEMS/MOEMS 6463-05.
• Thirumalesh Bannuru, Richard R. Chromik and Richard P. Vinci., “Internal oxidation and mechanical properties
of Pt-IrO2 thin films.” Poster presentation at Materials Research. Society conference, Boston, USA 2004
• Thirumalesh Bannuru, Richard R. Chromik and Richard P. Vinci., “Mechanical properties of dispersion (IrO2)
strengthened Pt films for piezoelectric MEMS applications.” poster presentation at the Center for Optical
Technologies - ARL Workshop on April 2004 at Lehigh University.
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