Design Engineer

ARVIND RAMAKRISHNAN ** OLD CART PATH

HOLLISTON MA

01746

Phone: 425-***-****

E-mail: ******.************@***.***

CAREER OBJECTIVE

To obtain a position as a Design/Verification engineer that provides an

opportunity to fully utilize acquired training and academic experience.

EDUCATION

Arizona State University

M.S, Electrical Engineering (Electronic & Mixed Signal Circuit Design)

December 2009

GPA: 3.8/4.0

Anna University, Chennai, India

B.E, Electronics & Communication Engineering, 2007

GPA: 3.5/4.0

TECHNICAL SKILLS

Simulation Software: MATLAB, Cadence Spectre, Modelsim, HSPICE

Design Languages/Tools: Verilog HDL, Cadence Virtuoso, Xilinx Tools

Programming Languages: C, C++, 80x86 Assembly language, PERL

Web Designing Skills: HTML, PHP, Dreamweaver

TECHNICAL PUBLICATION

. IEEE Publication titled "Multipath Interference Mitigation Technique

for MC DS/CDMA Systems" in the International Conference on "Control,

Automation, Communication and Energy Conservation", 2009.

WORK EXPERIENCE

Technology Support Specialist (November 2007- Present)

Intercollegiate Athletics, Arizona State University

. Setup and maintain the ASURITE network.

. Technical support for hardware, applications, operating systems,

networking and system integration.

. Document, track and monitor issues to ensure timely completion.

Research Assistant, Cellular Mobile Communication, Dept of ECE 2006-07

. Multipath Interference mitigation schemes for MC DS/CDMA systems to

preserve orthogonality and increase system throughput.

Student Intern

Airports Authority of India, Chennai, India (Jun 2005-Jul 2005)

. Analysis and working of the Baggage scanning machines and the Public

Announcement System.

Student Intern

Larsen & Toubro InfoTech, Chennai, India (May 2004-Jun 2004)

. Detailed study of Data Networking concepts.

. Implementation of project for Southern Railways of India in the form

of router installation for passenger reservation system.

Instructional Aide/Tutor

School of Mathematical and Statistical Sciences

. Tutor undergraduate students in groups or as individuals.

. Grade Assignments and post lectures, reminders and other relevant

information on the course website.

PROJECTS

Multipath Interference Mitigation Technique for High Speed Packet

Transmission in a WCDMA Downlink using Orthogonal Variable Spreading Factor

Codes

Investigated a realistic model that takes into consideration Multiple

Access Interference that causes severe degradation in signal. The proposed,

robust MPIM scheme in accession of turbo decoder is shown to have

performance close to Shannon's Limit as the number of iterations increases

thereby bringing down error rate in the presence of MAI.

Design of a 32*32 register file

Designed and layed out a 32*32 register file capable of read and write

operations through 2 read ports and 1 write port. The EDP was calculated on

both the schematic and extracted views of the circuit. The setup was

designed so as to achieve a minimum EDP value.

Design of a Cache simulator

Designed a cache simulator capable of implementing the snooping cache

reference protocol. The simulator was designed for 3 coherence states and 4

processors each having a 1Kb direct mapped cache.

Design of a pipeline simulator

Designed a simulator capable of implementing a 5 stage pipeline. The

simulator is capable of processing data transfer, arithmetic, branch and

meta instructions following a read of source registers in the second half

of the decode stage and writing to register file in the first half of the

write back stage.

Design of a 10 bit Pipelined Analog to Digital Converter Using Cadence

Virtuoso

Designed an analog to digital converter with 10, 1.5 bit RSD stages. The

individual blocks in the converter were written using Verilog-A and

parameters like gain, on resistance and capacitance scaled in successive

stages.

Design of a single ended folded cascode differential amplifier

Designed a folded cascode differential amplifier circuit using cadence

virtuoso tool in 0.35?m process for a supply of 2.7V. The amplifier

designed was built with a gain of 70 dB, phase margin of 68 degrees, unity

gain frequency of 26 MHz, CMRR of 55dB, slew rate of 10V/ sec and an output

swing of 2V. A common centroid layout was designed for the amplifier

circuit.

Design of a telescopic cascode differential amplifier

Designed a telescopic cascode differential amplifier circuit using cadence

virtuoso in 0.35?m process. The amplifier was designed for a gain of 60 dB,

gain margin of 27dB, phase margin of 58 degrees, unity gain frequency of 70

MHz, CMRR of 98.6dB and a slew rate of 74.8V/ sec.

RELEVANT COURSEWORK

Digital Systems & Circuits, VLSI Design, Analog Integrated Circuits,

Advanced Analog Integrated Circuits, Computer Architecture, Analog to

Digital Converters, Semiconductor Device Theory and Design of Experiments.

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