Engineer Design
Resume:
CAN V. NGUYEN
*** ****** ** *****, *********, CA 92028
*******@***.***
SUMMARY
Sr. Hardware Design Engineer / Project Engineer with expertise in
FPGA/ASIC Verilog design, high speed hardware board design, digital
signal processing, RF digital modulation, forward error correction,
TCP/IP protocols, MPEG and TV digital video. Background includes
CMOS VLSI IC design and Secret clearance while working at TRW.
TECHNICAL SKILLS
. Analog/digital circuit design. Product development technical
lead. Develop products from concept to production. System
architect, design tradeoff, design for test and
manufacturing ability, target cost, time to market.
. Complex FPGA Verilog design and simulation with Modelsim (Altera and
Xilinx)
. Digital Signal Processing
. MPEG2 and H.264/AVC. Digital video in 4:4:4, 4:2:2, 4:2:0
with 1080i, 1080p, 720p. Video compression using Magnum E5,
E6 chip set. Video decompression with BCM7320, BCM7400.
Graphic and VBI data insertion (CC 608/708, NABST, WST
Teletext, SID/AMOL, VITS, VITC). Transport multiplex,
demultiplex (rate convert, PAT/PMT replacement, PCR
correction). Local TV advertisement replacement/insertion.
MPEG over IP (1 Gbits Ethernet, IEEE 802.3z). TCP/IP with
Link, Internet and transport layers.
. RF digital modulation, OQPSK, QPSK, Link Budget, BER test,
Forward error correction encoding (Reed Solomon,
Interleaver, Convolutional encoding, Randomizer)
. Embedded Processor design with MC6800, BCM7320, BCM7400
processors. 33MHz, 32 bits PCI
. I/O interfaces: QPSK, OQPSK, 8PSK, DVBS2, 8-VSB, 64 and 256
QAM, DHEI, ASI, DS3, SMPTE 310, 10/100/1000 Ethernet, RS-
232, I2C.
. Design validation, failure analysis, system integration and
testing. Benchmark with rival products.
PROFESSIONAL EXPERIENCE
Pace, El Segundo, CA Principal Hardware Engineer July 2009
- Present
. Perform failure analysis on consumer satellite set top
boxes, make design modifications to improve or eliminate
failure rates. Product end to end system verification to
meet specifications. Pursue new product ideas and
feasibility studies for development.
. Designed the Xilinx (XC3S400-4FT256), ISE 11.1, VHDL and
Modelsim for Bit Error Rate verification.
Motorola, San Diego, CA Principal Staff Engineer
1992 - June 2009
Design Activities
. Performed circuit design, schematic capture and compilation
to generate layout net list. Verified component layout
footprints, supervised board layouts, critical nets,
component placements to optimize for trace routing length,
heat dissipation and noise isolation. Used Cadence Concept
for schematic capture, Allegro for layout.
. Employed host processor on the board to run embedded
software applications, hardware controls, configurations and
course of actions for detected faults.
. Designed FPGA with Verilog. Extensive use of Modelsim to
simulate the design. Maximized FPGA design functionalities
to reduce board level BOM cost.
. Developed test plans, manufacturing test procedures,
performed product system integration, design verification
using equipment such as MPEG transport analyzers, RF
spectrum analyzer, TCP/IP analyzer, video/audio parametric
measurements to validate design compliance to specifications
and industry MPEG, SMPTE formats/standards.
. Performed failure analysis at board and component level.
Design activities also included writing documents such as
product functional/parametric performance specifications and
design descriptions.
Design Projects
. Designed the SD and HD boards to perform MPEG4 (H.264) to
MPEG2 transcoder in Standard and High Definition for
commercial TV broadcast applications. The boards decoded
video with MPEG4 compression (1080i or 720p), re-encoding
the decoded video with MPEG2 compression in SD and HD. Also
included two AC3 Dolby compress audio pairs in the MPEG2
transport output.
. Designed many Satellite TV broadcast receiver
boards/products for customers like HBO, CBS, Fox, ESPN.
Multiple RF inputs such as QPSK, 8PSK and DVBS2.
. Designed FPGA to perform ASI transmitting and receiving of the
MPEG transport.
. Designed FPGA to perform video VBI data processing and
insertion (Closed Caption, NABST, WST Teletext, SID/AMOL and
VITS). Multiple FIR filters to shape the VBI waveform for
each data type to comply with standard.
. Designed FPGA to manipulate MPEG transport stream such as
rate converting, PCR correcting, PID filtering and aliasing.
. Designed FPGA to perform digital video processing for
formats/standards conversion and video graphic insertion.
. Designed FPGA to multiplex digital video/audio for SD-SDI
output and to interface with Gennum GS2972 for HD-SDI
output.
. Integrated Altera's 10/100 MAC megacore for the 10/100
Ethernet port (modem interface) to support remote access.
. Implemented MPEG over IP in FPGA, unicast or multicast, in
TCP / IP standard by encapsulation of the MPEG transport
packets into Ethernet datagram (1358 bytes with UDP, IP and
Ethernet headers). Integrated with Altera's 10/100/1000 MAC
to complete the Ethernet frame (8 bytes preamble, CRC) and
interface to 10/100/1000 Broadcom PHY.
. Designed the first MPEG2 High Definition Video/Audio decoder
board at Motorola (1080i and 720p video formats). Designed a
Xilinx FPGA to condition the transport input to HD video
decoder chip.
. Designed Motorola's DigiCipher II PML interface board for
Cable Headend and 8-VSB Terrestrial broadcast. Designed
Xilinx FPGAs to output transport in various standards and
data rates (SMPTE 310, ASI, DHEI, 64 and 256 QAM).
. Designed Motorola's DigiCipher II FPM board for commercial
TV signal transmission over Satellite. Digital and analog
mix signal board design. The board linked to the main
DigiCipher II encoder system through a Reed Solomon error
correctable DS3 network. Multiple Xilinx FPGAs on the board
to encode MPEG transport with forward error corrections
(Reed Solomon, Interleaver, Viterbi, and Randomizer).
Implemented digital numerical control oscillator technique
to perform QPSK/OQPSK modulation digitally. Hot swap and
built in fault detection circuitry for automatic redundant
switching.
TRW, Redondo Beach, CA MTS/Staff Engineer 1982
- 1992
. Worked on an ASIC design with VHDL which used
direct frequency hopping to avoid radar jamming
for avionic communication.
. Designed an interface board to perform high speed data
processing and formatting for Fiber Optic network interface.
. CMOS VLSI IC design engineer. Designed the FFT chip set to
perform up to 512 point FFT.
. Responsible for the design of the Key Generator
chip for secure serial data transmission.
. Worked on the Signal Processor Superchip.
Responsible for the MCU (micro control unit) macro
cell.
. Worked on the Convolver Superchip. Design Kernel
macro cell to performed 2 point convolution and
the I/O portion of the super chip.
EDUCATION
BSEE, University of Michigan, Ann Arbor, Michigan.
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