Engineer Design
Resume:
CHRISTOPHER PHAM
San Diego, CA 92129
C: 858-***-****
W: 775-***-****
H: 858-***-****
W-Email: abnbtu@r.postjobfree.com
H-Email: abnbtu@r.postjobfree.com
U.S. Citizen. Active Secret Clearance
SUMMARY:
. Expertise in digital and analog PCB design, high-speed transmission
line signal analysis and termination techniques, signal integrity,
clock distribution, systems integration, FPGA design, IC
qualifications, RF Analog circuit simulation and ASIC IO cell/package
electrical characterization.
. Experience in high-speed board systems architecture design, schematic
captures, RF Analog circuit simulation analysis, EMI/EMC (IPC-
2220/9592) design and test. Experience in cellular systems (WCDMA and
CDMA). Knowledge of custom ASIC design process, Intel 8051 Micro-
Controller, IO dies layout, IC package thermal characterization, test
equipment development and manufacturing process.
. Experience with Navy shipboard test rack designed for tactical data
communications Link16 and network communications. Familiar with
various military standard data (MIL-STD-1553, MIL-STD-461/704, DO-
254/178B, MIL-STD 6016C, IEEE-1394 and RS-232/422/485) and shipboard
test rack build (MIL-STD 2036A, 901D and 167). Experience with C4ISR
(POPKIN) System Architecture Design, Concept of Operation (CONOPS),
System Development, BOE-Risk Analysis, Technical Trade Studies, System
Management Requirements (DOORS-RTM tools), PDR, SDR & TDR processes.
. Knowledge and experience in project management, product presentation,
product competitive analysis, technical writing proposal, budget
planning, engineering technical management, QA Processes ISO9000, Six
Sigma and SPC lean process, DFT/DFM process, DVT and PCB manufacturing
qualification.
EDUCATION:
M.S.E.E. Northwestern Polytechnic University, Fremont, CA. Graduated in
Dec 1990
B.S.E.E. with Minor in Mathematics. California State University of Fresno.
Graduated in Dec 1987.
QUALIFICATIONS:
. Experience in Verilog HDL, Xilinx FPGA Design Tools, ABEL, OrCAD/PADS
Logic Schematic Capture, PADS Layout, Power PCB Expedition, Allegro
Board Layout, CAM350 Board Layout Verification, ViewLogic Xilinx XACT,
Cadence Spectra Quest, Ansoft HFSS, Mentor Graphics ICX, ADS/Genesys
RF 2000, C4ISR (POPKIN) System Architecture Design, RTM DOORS, Timing
Designer and HSpice.
. Fluent in usage of Oscilloscopes, Logic Analyzer, Network Spectrum
Analyzer, Digital Storage Oscilloscopes, Pulse Generator, High
Precision Multimeter and Time Interval Analyzer.
. Familiar with Microsoft Word, Excel, Power Point, Visio, AutoCAD Lite,
FoxPro, Data Analysis and Reduction Tools (DART), Oracle/Agile
Manufacturing Database, Microsoft Access, Microsoft Project Management
and Mac Pert Chart. Knowledge in UNIX, Windows 2000/NT, C/C++,
Fortran, LabView, Micro-Controller Assembly, Math Lab and SPC Chart
Runner.
EXPERIENCES:
Northrop Grumman Corporation, Fallon, NV. 12/09 -
Present
Senior Staff Digital Design Engineer 3.
. Perform digital or analog circuit design of TDCM electrical power
distribution and systems noise analysis. Generate schematic and
conduct schematic design review with internal design engineering
groups. Responsible for EMI/RF radar testing and data analysis of
main communication controller board. Support systems engineering
group integrate and troubleshoot hardware into the systems level and
hardware demonstrations at customer sites as requested.
Qualcomm Corporation, San Diego, CA. 04/07 - 09/09
Senior Hardware Design Engineer, Contractor. (Agency: Systems Pro Inc)
. Develop CDMA phones with the latest Qualcomm MSM (Mobile Station
Modems), Radio-One RF ICs, and power management devices for smart
phone and multimedia applications. Responsibilities include design
and analysis of analog, digital and RF for Agilent Verigy 93K ATE high
density PCB which involve ICT board-level digital, PMIC power
distribution, analog/digital design, RF analysis, and test
verification. Using Agilent ADS to perform cross simulation analysis
between LNA, Mixers, VCO, PLL, and Local Oscillators and board layout.
Generate and update schematic as design changed, allocate digital
test points for high speed digital channels, RF routing and digital
power supply assignment. Perform new components analysis for new
released products and update BOM/Schematic capture for release to
production. Perform failure analysis on engineering MSM production
and handler production test boards. Release finding test reports to
PTE and test engineering managers. Work with Compliance Engineer,
preparing test plan on prototype board to perform EMI/EMC compliance
testing and generate test report for internal review. Lead project
for the NI-Data Acquisition System (DAQ) test equipment rack
development for Delta Edge and Synax 2400 series for digital and RF
daisy chain handler production testers. Ongoing involvement with Lab
View and GPIB interface development for the Handler Testers.
Northrop Grumman Corporation, Redondo Beach, CA. 11/06 -
04/07
Senior Hardware System Design Engineer, Contractor. (Agency: Triple Crown
Consulting Inc)
. Perform loading, noise margin, IR drop and Spice circuit analysis on
the EEPROM reset control circuits and various interfaces for space
interface controller and power modules. Design power supply
distribution system for DC/DC converter and VRM implemented on board
traces routing guidelines. Work as part of the design team in the
design for test process for all EMC testing (EMI/RFI, EFT/B, ESD,
transient surge, power quality). Perform Spice PCB worst case
analysis and Linear Circuit simulation on low level analog design,
power/mixed signal coupling modes of PCB traces to determine and
predict EMI safety margin (EMISM) of intra-system EMI/EMC based on
specified RFP, interface control document (ICD) values and MIL-STD
461/462 & DO-254 requirement specification. Generate design solutions
to implement what filtering, shielding and power grounding to be
applied to achieve these predicted EMISM. Generate design and
analysis documents (D-Doc) for customer review. Provide design and
product failure analysis support.
Lockheed Martin Corporation, San Diego, CA. 10/03 -
11/06
Senior Hardware Design Engineer, Maritime Systems & Sensors.
. Determines and defines interface requirements between commercial and
military computers and radio communication equipment for Navy
shipboard communication equipment test rack. Familiar with Systems
Engineering and Verification Requirement Process (PDR, SDR, TDR &
CDRL), generate Link16- system interface architecture (ICDs), system
hardware specifications, operating procedures, test procedures for
electronic communication systems and perform technical trade study for
C2 and COMBATTS systems. Use AutoCAD/Visio to support rack/cable
hardware design changes or generate a diagram at the hardware (COTS
components), software and interface design level of detail for
implementation into the overall system architecture. Generate design
guideline for test rack power supply distribution system per ship 3-
phase power requirements. Conduct on ship board RF/MOS terminal
testing and Link-16 (MIDS) J messages data analysis at Navy bases test
laboratories (SPAWAR & Point Loma, San Diego). Familiar with MIL-STD-
1553, 2036, 6016C, 901D and RS-232/422. Supports system software
development both through high-level analysis and translation of system
requirements, and detailed analysis of signals and timing between
system components. Analyzes test results to further refine system
design. Generate BOE (Base of Engineering Estimate), Risk Mitigation
Study Analysis, System Interfaces Diagrams, Test Rack Hardware Bill of
Material BOM and System Integration Test Plans. Travel to Taiwan for
System of System Integration and Development Testing.
* Special Recognition Award: Link16-C2/TATDLS System Integration
Validation.
Viking InterWorks Corporation, Rancho Santa Margarita, CA.
05/03 - 10/03
Senior Systems Hardware Design Engineer, Contractor. (Agency: ICubed
Solutions Inc.)
. Provide on-site consulting services to train Engineers on use of
Mentor Graphics ICX simulation, and other Mentor Expedition tools that
support simulation. Trainees consist of approximately 4 design
engineers, 3 PCB layout engineers, and 3 DVT (Design Validation Test)
engineers. Perform SPICE and Mentor ICX worst case simulation of the
electrical circuits; evaluate the reliability of the design.
Coordinate verification testing reporting, and root cause analysis of
failures during development and testing. Work with product manager to
coordinate design reviews. Conduct software verification and EMI/RFI
compliance testing and analysis.
. Work with development engineering teams and designated test laboratory
on EMI issues at the PCB and system level, and analyze test results
with diagnosis of problems to recommend effective solutions. Perform
systems board level simulation and systems hardware software
integration. Assist internal Design Engineering Group in resolving
bus interfaces, timing design issues and define simulation test setup
parameters.
PROJECTS: Perform timing analysis, signal integrity and routing
guidelines for PC3200 DDR2 512Mb CSP memory
module. Develop IBIS and EBD models for 2 and 4 stacks DDR/DDR2 CSP
ceramic board.
Home Land Security/TSA, Oakland/San Diego International Airport.
11/02 - 05/03
Test Equipment Field Service Engineer
. Provide frontline security and protection of air travelers, airports
and airplanes. Primary Electrical Field Service Engineer for the
Invision Technology CTX System IED Bomb Scanner 2K Series, a non-
intrusive gamma radiation baggage inspection system. Responsible for
all system engineering integration including microcontroller scanning
sequence programming (object density/thermal), electrical issues,
design changes, system modifications and diagnostic support.
Calibrate and maintenance baggage XRAY scanner CTX 2500 and explosive
trace detection Barringer IOSCAN Itemiser 400B. Participate or
attendance in meetings where classified information is provided and
equipment updated information.
IBM Corporation, San Jose, CA. 08/01 - 08/02
Senior Systems Hardware Engineer, Contractor. (Agency: SoftBase Consulting
Corp.)
. Responsible for the topological design and signal integrity analysis
of network server platforms. Create HSPICE simulation decks, perform
pre-layout and post-layout signal integrity simulations, resolve all
signal quality and timing issues and perform signal integrity
measurements in the real system and correlate the measurement data to
the simulation results.
. Perform system PSB/FSB timing simulation and signal integrity for IBM
North Pole NP2S/NP4S products. Provide
timing simulation training and system support to system integrator
developer. Generate board routing guidelines,
verify board layout and prototype board signal quality test
verification.
PROJECTS: North Pole Program and develop timing and trace routing
guidelines for 350MHz bus PPC750/SRAM.
North Pole Orion II Program, sources synchronous signal timing
simulation, defines board stack-up and routing guidelines for 900MHz
systems bus interfaces.
Silicon Graphics Computer Systems Corporation, Mountain View, CA.
03/99 - 06/01
System Development Engineering Manager, HPS Division.
. Manage hardware design engineering group to develop graphics board
routing guidelines, timing/signal integrity
verification and custom ASIC DSP I/O characterization. Participate in
design review, product features presentation, prepare product design
budget, planning staffing needs, interview, hire and implement program
objective. Generate failure analysis test instructions to support
production lines.
. Review customer product requirements and create EMI/EMC test plans, or
review a pre-existing test plans, and work with internal application
engineer and customers to achieve mutually agreeable test plans and
strategies. Perform EMI/EMC design verification testing (DVT) that
subjects products to repeated functional, temperature, shock,
vibration, and exception testing. Develop Intel base 8051 Micro-
Controller to support manufacturing test software diagnostic.
. Provide guidance and training for printed circuit board design and
layout. Perform schematic capture and PCB layout using DX Designer
and Mentor PADs layout tool. Interface with PCB fabrication vendors,
implement component vendors selection criteria and generate system DVT
qualification reports to various design groups.
Generate system board diagnostic test software in C++ and micro
controller to support main server board DVT process.
PROJECTS: Develop timing and signal integrity generic routing
guidelines for 266Mhz I/O brick boards high speed
interfaces (PSB/FSB/SRAM). Design DSP high speed test boards layout
and generate custom DSP I/O characterization
process instructions for selected vendors.
ASIC Design Verification Engineer, NT Workstation Division, Project
Lead.
. Develop circuit board for IC devices characterization, performs Hspice
simulation for I/O cells verification and test
board signal integrity. Generate test report of the IC
characterization and provide written test procedure to IC vendors.
PROJECTS: Signal integrity HSpice simulation for memory, graphics
and I/O buses.
Quantum Corporation, Milpitas, CA. 01/88 -
03/99
ASIC Systems Interface Design Engineer, Project Lead.
. Design and develop test board for I/O cells verification of ASIC high-
speed sub-micron digital CMOS. Perform I/O package signal integrity
analysis, board routing timing from drive interface to systems
controller, generate drive PCB/IO test board schematics and PCB
routing guidelines.
. Define I/O cell test specifications, perform electrical analysis, I/O
modeling simulation, FPGA functional and timing simulation, execute
functional test to evaluate the devices functionality and analyze dev
ices failure modes. Publish the written reports of the testing and
coordinate the testing projects with other divisions.
PROJECTS: Design Failsafe Tester for CMOS latch-up using FPGA
devices
Develop HP-IBASIC test program to automate impedance test processes.
. Analyze test data and resolve EMC technical issues. Review test
specifications. Develop product test plans and identify and procure
test equipment. Interface with internal and external design teams and
customers. Develop EMC guidelines and procedures. Develop stand lone
tester, create test board schematics, generate board stack-up and
routing guidelines for specific OEM qualification of high speed PCBA,
participates in customer design review and test board qualifications.
PROJECTS: 2.5" and 3.5" drives IDE interface DS/CS Jumper Tester.
3.5" drive SCSI Interface Termination Enable Tester.
*Quantum Patent: 2.5" and 3.5" drives IDE interface DS/CS Jumper
Tester.
. Design or redesign circuits, troubleshoot and maintain servo writer,
head/media tester for new or existing products.
Perform evaluation of product design and development of verification
testing. Document results of qualification
efforts and publish results to interested parties. Represent
manufacturing in test equipment design issues, new test process, servo
test board schematics modification and manufacturing implementation.
Develop drive diagnostic test code by formulate drive test modules and
implement in C. Provide customer support, recommend design change for
drive test equipment to meet the need of newly released products and
review hardware/software for areas of improvements. Travel
extensively to Singapore and Thailand.
REFERENCES: Furnish upon request.
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