Project Engineer

Embedded Application Developer

Naga Sowjanya Merugu ) +91-812******* Email:

**********@*****.***

Seeking a responsible and rewarding position in an esteemed organization

with challenging work environment.

SYNOPSIS

< M.Tech (Computer Science) from SIT, JNTU, Hyderabad.

< Working as a Embedded Application Developer in CSIR-CEERI, Pilani.

< Exposure in RTOS & FPGA Domain.

< Involved in project lifecycle and worked closely with Application design

engineer.

< A self-motivated hard worker with good communication skills.

EXPERIENCE

Organization Designation Duration

Central Electronics Project Assistant March 2009 - March 2012

Engineering Research

Institute(CEERI)

GEENI Technologies Teaching April 2007- January

2008

NIIT Teaching April 2008 - June 2008

ACADEMIC CREDENTIALS

Qualification Institution/University Year of %

passing Scored

M.Tech(CS) JNTU, Hyderabad 2008 65

B.Tech (CSE) JNTU 2005 56.49

Diploma(DCME) State Board Of Technical 2002 60.1

Education And Training,

A.P, Hyderabad

X Board Of Secondary 1998 66.6

Education, A.P

TECHNICAL SKILLS

Primary skills Embedded C, VxWorks, BSP, JTAG, FPGA

Standards/Protocols SIP, TCP/IP

Additional skills C++, VHDL, Matlab, OS CONCEPTS, RDBMS, HTML,

JAVASCRIPT, ALGORITHMS AND DATASTRUCTURES, MS

Word, SQL Server 2000.

Domain Knowledge RTOS

Tools Xilinx, Wind River Workbench 2.5

Certification SKILLS

< Board Support Package (BSP) and Embedded System Software Development

training from Wind River.

AREAS OF EXPOSURE

< Good knowledge of Embedded C.

< Familiar with VxWorks, Board Support Package (BSP), Drivers, Boot Loader,

Xilinx FPGAs based boards and JTAG debugger.

PROJECTS PROFILE

< A premier R & D Institute in India, in the field of Electronics and

Communication under CSIR and working for different sponsored (either from

Industry or Govt. agencies) R & D projects, making the Indian Industries

aware of the latest and future technologies.

Project Profile - 1

Project Name : Implementation of scheduling algorithm with different

partial bit streams on FPGA using EDK

Client : SIP-021 (CSIR Project)

Organisation : CSIR-CEERI

Details : This method of Partial Reconfiguration is accomplished by

making a small change to a design (normally done in FPGA_Editor), and then

by generating a bitstream based on only the differences in the two designs.

Switching the configuration of a module from one implementation to another

is very quick, as the bitstream differences can be extremely smaller than

the entire device bitstream.

Role . Involved in requirement gathering & analysis.

. Using Xilinx provided Device drivers of interfaces UARTLite,

I2C, SPI, PCI, DDR, Ethernet Core, System ACE

. Embedded C for Application Development

. Bug Solving through the JTAG and verification of the

Application.

Project Profile - 2

Project Name : Implementation of customized VxWorks 6.3 BSP for the IBM

PowerPC 405 and System Image Creation for the

BSB DDR2 Design Using EDK 10.1i SP3

Client : SIP-021 (CSIR Project)

Organisation : CSIR-CEERI

Details : This Project describes automatic generation of a VxWorks 6.3

Board Support Package (BSP) for the IBM PPC405 and its peripherals as

defined within a Xilinx Platform Studio (XPS) on FPGA.

1). Generating and modifying BSP for ML410 which should be for VxWorks

(RTOS).

2). Using the above BSP creating an image in workbench 2.5.

3). Porting RTOS such as VxWorks into the PowerPC which is available

with Virtex-4 FPGA.

4). Program written in C (using VxWorks 6.3 simulator) should

run on PPC 405.

Role . Involved in requirement gathering & analysis.

. Modifying Xilinx provided Device drivers of interfaces

UARTLite, I2C, SPI, PCI, DDR, Ethernet Core, System ACE

. Embedded C for Application Development

. Bug Solving through the JTAG and verification of the

Application.

Project Profile - 3

Project Name : Implementation of list scheduling algorithm on VxWorks

simulator.

Client : SIP-021 (CSIR Project)

Organisation : CSIR-CEERI

Details : In This Project development of scheduling algorithms

implementation using Xilinx embedded development kit (EDK) with and without

support real-time operating system (VxWorks). The main objective is to

optimize the execution time of the given application in the form of coarse-

grain directed acyclic graph (DAG). Scheduling algorithm implemented using

Partial Reconfiguration for Task scheduling for Cut-Tree, Fork-Join, FFT,

Mean-Value34, and Mean-Value36 of Different Partial bit streams (according

to our Partial Reconfiguration Regions) on FPGA using EDK.

Role . Involved in requirement gathering & analysis.

. Using Xilinx provided Device drivers of interfaces UARTLite,

I2C, SPI, PCI, DDR, Ethernet Core, System ACE

. Embedded C for Application Development

. Bug Solving through the JTAG and verification of the

Application.

Project Profile - 4

Project Name : Image reading using C language (Image Processing)

Client : SIP-021 (CSIR Project)

Organisation : CSIR-CEERI

Details : In this Task implemented the Image reading on FPGA using

EDK.

Role . Involved in requirement gathering & analysis.

. Using Xilinx provided Device drivers of interfaces UARTLite,

I2C, SPI, PCI, DDR, Ethernet Core, System ACE

. Embedded C for Application Development

. Bug Solving through the JTAG and verification of the

Application.

Academic Projects

Project Profile - 5

Project Name : User Agent Implementation in SIP (Session Initiation

Protocol)

Organisation : Sapera Systems

Technology : VOIP

Details : This Project describes implementation of User Agent in

Session Initiation protocol (SIP). SIP is an application-layer control

(signaling) protocol for Creation, modifying, and terminating sessions with

one or more participants. These Sessions include Internet telephone calls

and multimedia conferences.

Role . Involved in requirement gathering & analysis.

. Developed C code for SIP protocol on Linux.

. Software Designing

. Bug Solving through and documentation.

Project Profile - 6

Project Name : XML parser and Rendering Agent

Environment : Java, XML

Duration : Two months

Details : The main purpose of this project is to construct AWT

components Like Frames, Buttons, text, fields etc. to be composed from XML

Document .Now a day's XML is a Defacto standard of data transfer between

the communication processes.

Role .Involved in requirement gathering & analysis.

.Developed HTML and Java Script code for webpage.

.Software Designing.

. Documentation.

PERSONAL DETAILS

Father's Name M. Anjaneyulu

Pan Card Number DPGPS6314F

Date of Birth 5th, May, 1983

Nationality Indian

Languages Known English, Hindi and Telugu

Marital status Unmarried

Present Address H-No: 1-1/17A, Nehrupet, Nuzvid, Krishna

District, A.P

I hereby declare that all the information given above is true to my

knowledge.

PLACE: Hyderabad M. Naga Sowjanya

DATE:

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